1. Altera Technical Solutions Seminar 2000

2. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap Quartus Demo

3. Agenda Introduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap u NativeLink™ Integration u Scripting

4. Integration with EDA Partners Place & RouteDesign Verification Synthesis Synopsys Synplicity Exemplar Logic EDA Partner Model Technology/ Mentor Graphics Cadence Synopsys EDA Partner EDIF Verilog VHDL SDF EDIF Verilog VHDL AHDL Quartus

5. NativeLink EDA Integration  Seamless Interfaces with Popular Tools EDA Tools Can Run Seamlessly in Quartus EDA Tools Can Run Seamlessly in Quartus Quartus Can Run Seamlessly in EDA Tools Quartus Can Run Seamlessly in EDA Tools  Improved Utilization and Timing Prediction Available for Synthesis Tools Run-Time Access to Quartus Device and Project Databases Run-Time Access to Quartus Device and Project Databases

6. Adaptive Timing-Driven Synthesis Constraints Quartus Place and Route Netlist Extraction Synthesis Tool Tech Mapping Synthesis

7. Scripting Capabilities  Two Powerful Scripting Languages Visual Basic Visual Basic TCL/TK (Platform Independent) TCL/TK (Platform Independent)  Total Automation A Single Script Can Run an EDA Tool and Quartus A Single Script Can Run an EDA Tool and Quartus Customize Output to Suit Specific Needs Customize Output to Suit Specific Needs Customize Input Settings in a Spreadsheet or Text File Customize Input Settings in a Spreadsheet or Text File

8. ModelSim PE - Highlights  100% VHDL,Verilog Support Supported on all Platforms (98, NT, Solaris, HP) Supported on all Platforms (98, NT, Solaris, HP) Testbench Support Testbench Support “Behavioral” Constructs Support “Behavioral” Constructs Support  HDL Debugging Environment HDL Compiler, Simulator, Source Editor, Waveform viewer, Dataflow Manager HDL Compiler, Simulator, Source Editor, Waveform viewer, Dataflow Manager  Optimized Direct Compiled Architecture Compiles HDL directly to machine independent object code Compiles HDL directly to machine independent object code  Tcl Scripting Support  Integration w/ other EDA tools in the industry Quartus, MP2, Renoir, Leonardo Spectrum etc. Quartus, MP2, Renoir, Leonardo Spectrum etc.

9. FPGA Express Features  Architecture-specific mapping for high QoR ATOMs (I/O, Lcell, etc.) ATOMs (I/O, Lcell, etc.) Carry/cascade chains Carry/cascade chains  LPM inferencing Multiplier LPMs inferred for FLEX and APEX devices Multiplier LPMs inferred for FLEX and APEX devices Other arithmetic operators are implemented using ATOMs and carry chains Other arithmetic operators are implemented using ATOMs and carry chains  Automatic Global Signal Mapping

10. FPGA Express Features  TimeTracker Spreadsheet-based timing analysis tool Spreadsheet-based timing analysis tool Saves time by catching timing issues before P&R Saves time by catching timing issues before P&R  VisTA Schematic Viewer Tightly linked with TimeTracker for graphical analysis Tightly linked with TimeTracker for graphical analysis Analyze RTL and optimized design schematics Analyze RTL and optimized design schematics  Easy-to-use Synthesis Control Push-button flow Push-button flow Constraint-based flow Constraint-based flow Hierarchical flow Hierarchical flow Script-based flow Script-based flow

11. DesignWare FPGA Express DC Shell.db Push-Button Flow Industry-Standard HDL Support Built-In Static Timing Analysis Tool Schematic Viewer Integration with MAX+plus II & Quartus FPGA Compiler II (Altera Edition) FPGA Express FPGA Express Vs FPGA Compiler II Retiming  What is FPGA Compiler II Altera Edition ?

12. FPGA Compiler II - Altera Edition  Superset of FPGA Express Plus...  Design Ware Support: FC II Altera edition supports the DesignWare  Foundation components. FC II Altera edition supports the DesignWare  Foundation components. Instantiated DesignWare components are synthesized using FC II with no user intervention. Instantiated DesignWare components are synthesized using FC II with no user intervention. FCII Does not infer DesignWare components, FCII Does not infer DesignWare components, Uses a Built-in module generator to infer the optimal operator. Uses a Built-in module generator to infer the optimal operator. .db File Support: FCII can export a DB File to Primetime or DC or Formality FCII can export a DB File to Primetime or DC or Formality

13. FPGA Compiler II - Altera Edition  DC Shell Script translation Helps easy ASIC -> FPGA Migration: Helps easy ASIC -> FPGA Migration: Most DC users utilize the scripting capability to automate their design flow. Most DC users utilize the scripting capability to automate their design flow. Utility to help these designers migrate to FC II Utility to help these designers migrate to FC II fc2_altera_shell > translate_dc_script – input_script dc_shell.scr –output_script fc2.scr fc2_altera_shell > translate_dc_script – input_script dc_shell.scr –output_script fc2.scr –where dc_shell.scr is the original dc_shell script and fc2.scr is the translated script.  All GUI Actions in FCII have an Equivalent shell command

14. Leonardo Spectrum Update  Device Support Update: 1999.1h:MAX 7000 A/E/S Support 1999.1h:MAX 7000 A/E/S Support 1999.1i: MAX 3000 Support 1999.1i: MAX 3000 Support 2000.1: ACEX Support (in the April time frame) 2000.1: ACEX Support (in the April time frame)

15. Leonardo Spectrum Update  1999.1 I/O Register Packing: Default to OFF Default to OFF Set from the Technology Form Set from the Technology Form Will Bring Internal Flops into the I/O ATOMs Will Bring Internal Flops into the I/O ATOMs Technology Form Unpacked Packed

16. Leonardo Spectrum Update  1999.1i: PTERM Optimization for APEX LCELL PTERM Allows full utilization of the APEX architecture!  PTERM Constraint Set on Instance  Implemented as Sum-of-Products Logic  Quartus Instructed to Implement in PTERMs through Native-Link (passed as Tcl Constraint)

17. Leonardo Spectrum Update  Coming in 2000.1a Beta in March 2000 Beta in March 2000 Production in April 2000 Production in April 2000 New Schematic Viewer (Leonardo Insight) New Schematic Viewer (Leonardo Insight) Integrated Design Browser Integrated Design Browser  Also coming in 2000 In-Place Optimization Flow In-Place Optimization Flow Re-optimize critical paths after place and route Re-optimize critical paths after place and route Optimize the “real critical paths “ Optimize the “real critical paths “ Reduce design iterations through place and route Reduce design iterations through place and route

18. Benchmark Score (23 designs,win point) 3:8:12 1:9:134:14:5 TDC Off 5:7:111:10:123:13:7 TDC On TimeArea f MAX FC2 : Synplify : Leonardo

19. EDA Integration Summary  Quartus Fits Seamlessly into Existing Flows Can Work Under the Command of Other Tools Can Work Under the Command of Other Tools Can Launch Other Tools and Vice Versa Can Launch Other Tools and Vice Versa  Tools Can Communicate with Each Other Constraints and Results Can Be Passed Between Tools Constraints and Results Can Be Passed Between Tools  CAD Managers Can Script Custom Flows