1. Under the Guidance of Dr. Meghana Kulkarni Prof. Abhishek Deshmukh MRS. VAISHALI B BHENDIGERI Presented by 3-D (IC)chip technology

2. 3-D Chip Design Challenges To maintain the overall pace according to Moore’s law requires an acceleration of packaging development companies have driven 3D packaging envelopment in the past few years but thermal aspects and high density interconnects have been neglected in those applications. While 2D scaling has been used in high performance processors over several decades, the third dimension has not yet been tackled. The need to pack more transistors into a single package is becoming a needed necessity. There’s a big demand, in the consumer market, for smaller packages and in order to meet this demand, 3-D chip technology must be perfected.

3. 3-D chip technology

5. Oxide Material For 40 years, the SiO2 gate oxide combined materials for scaling MOS devices down to the 90nm technology node. Starting with the 90nm technology, SiO2 has been replaced by SiON dielectric, which features a higher permittivity and consequently improves the device performances while keeping the parasitic leakage current within reasonable limits. 3-D chip technology

6. Starting with the 45-nm technology, leakage reduction has been achieved through the use of various high-K dielectrics such as Tantalum Oxide Ta2O5 (er=25) or Titanium Oxide TiO2 (er=40). This provides much higher device performance as if the device was fabricated in a technology using conventional SiO2 with much reduced “equivalent SiO2 thickness”. The high-k transistors feature outstanding current switching capabilities together with low leakage.. 3-D chip technology

7. The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. Table 1 gives an overview of the key parameters for technological nodes from 180 nm, introduced in 1999, down to 22 nm, which is supposed to be in production around 2011. 3-D chip technology

8. Methods To Dissipate Heat Generated In 3D IC

9. Scaling Benefits The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. Table 1 gives an overview of the key parameters for technological nodes from 180 nm, introduced in 1999, down to 22 nm, which is supposed to be in production around 2011. the average distance between system components is reduced, which in turn will improve the performance, but the challenge to remove the heat is multiplied by the number of layers in the integration of the micro-cooling channels between the silicon vias. 3-D chip technology

10. The temperatures within the 3D-IC system have to remain below 90°C during operation to avoid damage to the chip. The objective of the coolant is to maintain the chip’s temperature at of 30-40°C. The objective of limiting the temperature of the chip and having a uniform temperature distribution is reached by letting flow liquid coolant (doped with nano-particles) in micro-channels with micro-pin elements to enhance heat transfer from the solid to the fluid. 3-D chip technology

12. 3D stacked MPSoC architecture with interlayer microchannel cooling;

13. 3-D chip technology

15. Advantages The 3D chip design technology can be exploited to build SoCs by placing circuits with different voltage and performance requirements in different layers. The 3D integration can reduce the wiring,thereby reducing the capacitance, power dissipation and chip area and therefore improve chip performance. Additionally the digital and analog components in the mixed-signal systems can be placed on different Si layers thereby achieving better noise performance due to lower electromagnetic interference between such circuits blocks. From an integration point of view, mixed-technology assimilation could be made less complex and more cost effective by fabricating such technologies on separate substrates followed by physical bonding.

16. Conclusion 3D ICs are an attractive chip architecture, that can alleviate inter connect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip. The multilayer chip building technology opens up a whole new world of design like a city skyline transformed by skyscrapers, the world of chips may never look at the same again.

17. References Chau-Jie Zhan, Jing-Ye Juang, Yu-Min Lin, Yu-Wei Huang, Kuo-Shu Kao, Tsung-Fu Yang, Su-Tsai Lu, Lau, J.H., Tai-Hong Chen, Lo, R., Kao, M.J., "Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead- free solder micro bumps and reliability characterization", Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, On page(s): 14 - 21 Bing Dang, Shapiro, M., Andry, P., Tsang, C., Sprogis, E., Wright, S., Interrante, M., Griffith, J., Truong, V., Guerin, L., Liptak, R., Berger, D., Knickerbocker, J., "Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru- Si Via Interconnects", Electron Device Letters, IEEE, On page(s): 1461 - 1463 Volume: 31, Issue: 12, Dec. 2010 Jaesik Lee, Seetoh, J., Hong Yu Li, Lee, V., Yen Chen Yeo, Guan Kian Lau, Keng Hwa Teo, Shan Gao, "Compatibility of Dielectric Passivation and Temporary Bonding Materials for Thin Wafer Handling in 3-D TSV Integration", Components, Packaging and Manufacturing Technology, IEEE Transactions on, On page(s): 1988 - 1995 Volume: 1, Issue: 12, Dec. 2011 Kwang-Seong Choi, Ki-Jun Sung, Byeong-Ok Lim, Hyun-Cheol Bae, Sunghae Jung, Jong Tae Moon, Yong Sung Eom, "Novel bumping material for stacking silicon chips", Electronics Packaging Technology Conference, 2009. EPTC '09. 11th, On page(s): 579 - 583

18. Thank you