1. DHH progress report Igor Konorov TUM, Physics Department, E18 DEPFET workshop, Bonn February 7-9, 2011 Outline:  Implementation synchronous clock distribution using Xilinx V5 GTP  Summary and outlook

2. Why Xilinx FPGA Motivation to use Xilinx FPGA instead of Lattice FPGA –Belle II RO electronics and ATCA based on Xilinx FPGAs –New IHEP ATCA design utilizes SFP+ and FPGAs capable to run up to 6 Gbps –KEK colleagues study Xilinx FPGA SEU in neutron irradiation –Xilinx FPGAs radiation tolerance should be higher due to partial reconfiguration capability DEPFET workshop, Bonn И.Коноров, TUM 2

3. Synchronous clock distribution Δ T must be constant RX: Recover clock from data Align recovered clock phase to byte boundaries using COMMA symbols(8b/10b) No FPGAs with fixed latency requirement DEPFET workshop, Bonn И.Коноров, TUM 3 ΔTΔT SerializerDeserializer TXRX 16 bits

4. Virtex5 SERDES latency Xilinx UG196: The latency of the blocks is deterministic with the exception of the RX elastic buffer (64-element FIFO) and the TX buffer (4-element FIFO). Bypassing buffers requires marginal conditions to be met, for example, phase alignment procedures or USRCLK requirements. DEPFET workshop, Bonn И.Коноров, TUM 4

5. Test setup DEPFET workshop, Bonn И.Коноров, TUM 5 TX SYNC PULSE RX SYNC PULSE

6. RX Clock phase scan DEPFET workshop, Bonn И.Коноров, TUM 6 Clock phases after applying multiple RX reset

7. Virtex5 GTP(SERDES) GTP RX deserializer RX CDR – Clock Data Recovery 1.RX clock (recovered) aligned to any bit in 10 bit word 2.COMMA alignment using logic wo realigning RX CLOCK phase DEPFET workshop, Bonn И.Коноров, TUM 7

8. Deserializer synchronization circuit RX0 – time reference RX RX1 – being synchronized RX Synchronization procedure 1.Reset RX1 until maximum clock phase difference detected 2.Reset RX1 until one predefined(earliest) clock phase detected DEPFET workshop, Bonn И.Коноров, TUM 8 RX0 RX1 Phase alignment logic FPGA RX RESET

9. Link synchronization Synchronization procedure 1.Synchronize TX 2.Synchronize RX1 Status : –VHDL code developed and tested DEPFET workshop, Bonn И.Коноров, TUM 9 RX0 RX1 Phase alignment logic FPGA RX RESET TX RX Phase alignment logic FPGA RX RESET TX RESET

10. Summary Virtex 5 GTP features evaluated and allow to implement synchronous link VHDL code for synchronous link implementation complete Long term test to be done DEPFET workshop, Bonn И.Коноров, TUM 10

11. Outlook Questions: –DHP  DHH cable interface –Slow control and online data processing Reading full frame Pedestal calculation Pedestal loading via JTAG Reading full frame via JTAG an option? DHH system design to be finalized later Next steps (mostly VHDL code development using ev.cards) –DHH  ATCA - discussion with Soeren and Zhen’an –DHP  DHH – discussion with Hans –DHH module schematic DEPFET workshop, Bonn И.Коноров, TUM 11