1. 0 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) The Industry’s Fastest Quad SPI NOR Flash Memory Family for High-Performance Embedded Systems New Product Introduction: 128Mb to 1Gb Quad SPI FL-S NOR Flash Family FL-S = Cypress’s 3.0-V, 65-nm NOR Flash Memory Family With MirrorBit ® 1 Technology Title 1 Cypress Nonvolatile Memory cell technology with two localized electron storage locations to provide two data bits per cell, effectively doubling the NOR Flash Memory density

2. 1 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) NOR Flash Memory Terms Nonvolatile Memory (NVM) A memory that retains data even when it is not powered Program Memory A low-latency and high-bandwidth NVM that enables fast execution of CPU instructions Flash Memory An NVM that alters the voltage at which a transistor conducts current by adding or removing electrons to set predefined “1” and “0” states for a memory cell NOR Flash Memory A Flash Memory with a memory architecture optimized for fast, low-latency random access (vs. fast consecutive address access) MirrorBit ® Cypress NVM cell technology with two localized electron storage locations to provide two data bits per cell, effectively doubling the NOR Flash Memory density Read Bandwidth The measurement of how fast data can be read from a memory, expressed in bytes per second Serial Peripheral Interface (SPI) An industry-standard, low-pin-count interface used in embedded systems that enables synchronous data exchange (1 bit per cycle) between a master and slave device(s) Quad SPI An industry standard, high-bandwidth, low-pin-count interface that simultaneously uses a four-wire SPI interface to enable faster data transactions Terms of Art

3. 2 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Additional NOR Flash Memory Terms Single-Data-Rate (SDR) A mode of data transfer in which data is transferred once per clock cycle Double-Data-Rate (DDR) A mode of data transfer in which data is transferred twice per clock cycle Program/Erase The operation required to change a NOR Flash Memory cell state from “1” to “0” or from “0” to “1”, respectively Sector A physical block of memory locations with consecutive addresses (e.g., a 4KB sector in a 256Mb memory) Sector Erase The operation in which all the bytes in a Sector of NOR Flash Memory are Erased simultaneously prior to Programming Chip Erase The operation in which all memory cells in the NOR Flash Memory are Erased prior to Programming Terms of Art

4. 3 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) The market for 256Mb SPI 1 NOR Flash Memory is projected to grow at an 8% CAGR, from 112 million units in 2015 to 192 million units in 2021 2 256Mb SPI NOR Flash Memory market segments: Advanced driver assistance systems (ADAS) Automotive instrument clusters Automotive infotainment systems Networking devices Set-top boxes OEMs in these market segments design high-performance systems that require fast NOR Flash Memory for both Program execution and data storage functions Designers of high-performance systems prefer NOR Flash Memory with: A low-pin-count serial interface to reduce package size and to simplify board layout The highest Read Bandwidth to quickly access Program Memory The fastest Program and Sector Erase speeds to quickly write data Designers of high-performance systems require fast, low-pin-count Quad SPI NOR Flash Memory Market Vision 1 Includes SPI and Quad SPI NOR Flash Memories 2 Source: Web-Feet Research High-Performance Systems Need Fast, Low-Pin-Count NOR Flash Memory Automotive Infotainment System by Alpine

5. 4 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Cypress: No. 1 in NOR Flash, SRAM, NVRAM Comparison to Competitors’ Memory Product Portfolios Cypress has the broadest portfolio of high-performance memories for embedded systems Product CategoryCypressCompetitorsPerformance Advantage Metrics ISSIMicronToshibaWinbondMacronixFujitsu No. 1 NOR Flash Parallel NOR Flash Highest Read Bandwidth Fastest Program/Erase 102 MBps Serial NOR Flash Highest Read Bandwidth Fastest Program/Erase 160 MBps HyperFlash™ 1  Highest Read Bandwidth333 MBps No. 1 SRAM QDR ® -IV Synchronous SRAM  Highest RTR (random transaction rate) 2.1 GT/s Asynchronous SRAM with ECC 2  Highest reliability<0.1 FIT 3 MicroPower SRAM Lowest standby current1.5 µA No. 1 NVRAM Serial F-RAM™ 4  Lowest standby current100 µA Parallel nvSRAM 5 Fastest NVRAM 6 20 ns AGIGARAM ® 7 Highest-density NVRAM 6 16GB 1 A Cypress NOR Flash Memory product family that offers higher bandwidth than Quad SPI NOR Flash Memory with one-third the number of pins of parallel NOR Flash Memory 2 Error-correcting code 3 Failures In Time (billion hours) 4 Ferroelectric RAM Market Positioning 5 Nonvolatile SRAM 6 Nonvolatile memory that provides direct access to read and write to any memory location in any random order 7 A Cypress brand name

6. 5 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) NVM Problems Designers Face 1. Many high-performance portable system designs require a small PCB Traditional 256Mb parallel-interface NOR Flash Memory requires a 56-pin package (280 mm 2 ) and a large PCB area 2. Systems require the highest Read Bandwidth for Program execution Low NOR Flash Memory Read Bandwidth diminishes system performance Traditional 256Mb Quad SPI NOR Flash Memory products have Read Bandwidth as low as 52 MBps 3. Systems require the fastest Program and Sector Erase times possible Slow Programming time decreases PCB manufacturing throughput Traditional 256Mb Quad SPI NOR Flash Memory products are limited to a Program time of 0.5 ms per 256 bytes Systems must conduct a Sector Erase prior to writing new data into NOR Flash Memory Traditional 256Mb Quad SPI NOR Flash Memory products may have Sector Erase times as high as 700 ms 4. Automotive applications require AEC-Q100 qualified products Traditional 256Mb Quad SPI NOR Flash Memory products are not AEC-Q100 qualified Cypress’s 256Mb Quad SPI NOR Flash Memory solves these problems by providing: A Quad SPI interface NOR Flash Memory in either an 8-pin (48-mm 2 ) or 24-ball (48-mm 2 ) package to simplify board layout An 80-MHz DDR mode with 80-MBps Read Bandwidth A 0.25-ms Program time per 256 bytes A 130-ms Sector Erase time An AEC-Q100 qualification Design Problems Cypress offers the industry’s fastest 256Mb Quad SPI NOR Flash Memory for high-performance systems

7. 6 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Cypress Quad SPI NOR Flash Memory: A Better Solution To produce the highest- performance solutions for high-performance applications. Cypress Solution Choose the NOR Flash Memory that combines the industry’s highest Quad SPI Read Bandwidth… With the industry’s fastest Quad SPI Program time and … Set-top Box by Sky TV Read Bandwidth (MBps)Program Time (ms)Sector Erase Time (ms) Fastest Sector Erase times… CypressMicronMacronixWinbondCypressMicronMacronixWinbondCypressMicronMacronixWinbond

8. 7 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) FeatureS25FL256SN25Q256A13W25Q256FVMX25L25635F SPI Clock Rate (SDR) QIO 1 104 MHz108 MHz104 MHz133 MHz Read SDR QIO 1 Bandwidth (max) 52 MBps 2 54 MBps 2 52 MBps 2 67 MBps 2 SPI Clock Rate (DDR) 80 MHz54 MHzNot Supported Read DDR Bandwidth (max) 80 MBps 3 54 MBps 3 Not Supported Program Time (256B) 4 0.25 ms0.5 ms0.7 ms0.5 ms Sector Erase Time (64KB) 4 130 ms700 ms150 ms280 ms Chip Erase Time 4 66 s240 s80 s110 s Temperature Range -40ºC to +125ºC -40ºC to +85 º C Cypress 256Mb Quad SPI NOR Flash Memory vs. Competition’s 1 Quad input/output (QIO): An interface that transfers addresses or data on four I/O’s simultaneously 2 Calculated using SDR clock rate with QIO divided by two 3 Calculated using DDR clock rate with QIO 4 Conditions: 25ºC and V CC 3.0 V Competitive Comparison

9. 8 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Sampling: Now Production:Now Cypress’s 256Mb (FL256S) Quad SPI NOR Flash Memory Advanced driver assistance systems (ADAS) Automotive instrument clusters Automotive infotainment systems Networking devices Set-top boxes Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 20-year data retention at +55°C SDR 4 clock rate: 104-MHz QIO 5 DDR 6 clock rate: 80-MHz QIO 5 Program 1 time (256B): 0.25 ms (typical) Sector Erase 2 time (64KB): 130 ms (typical) Industrial temp range (AEC-Q100 opt.): -40°C to +85°C Industrial plus temp range (AEC-Q100 opt.): -40°C to +105°C Extended temp range (AEC-Q100 opt.): -40°C to +125°C Packages: 16-SOIC 300 mil, 8-WSON 7 6 mm x 8 mm, 24-ball BGA 6 mm x 8 mm Features Datasheet: S25FL256SS25FL256S Download App Note: Cypress FL-S SPI NOR Flash MemoryCypress FL-S SPI NOR Flash Memory Collateral Block Diagram Availability 5 Quad input/output (QIO): An interface that transfers addresses or data on four I/Os simultaneously 6 Double data rate: A mode of data transfer in which data is transferred twice per clock cycle 7 Very, Very Thin, Small-Outline, No-Lead semiconductor package 8 Signals used for standard Quad (x4) SPI interface; refer to the S25FL256S datasheet for signalS25FL256S definitions in the x1 and x2 mode 9 RESET# is an optional signal available on 16-SOIC and BGA packages 10 Read data buffer Product Overview 256Mb Quad SPI NOR Flash Memory SRAM I/O Array Left Control Logic RD 10 Array Right Data Path X/Y Decoder 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation required prior to a NOR Flash Memory Program, in which all the bits in a Sector are set to value “1” 3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it wears out 4 Single data rate: A mode of data transfer in which data is transferred once per clock cycle CS# 8 SCK 8 IO0 8 IO1 8 IO3 8 IO2 8 RESET# 9

10. 9 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) SPI NOR Portfolio S25FL2-K 90nm, 3.0V S25FL1-K 90nm, 3.0V S25FS-L 65nm, 1.8 V S25FL-L 65nm, 3.0V S25FL-P 90nm, 3.0 V S25FS-S 65nm, 1.8 V S25FL-S 65nm, 3.0 V S79FL-S 65nm, 3.0 V 32Mb 104 MHz / -- * I, IA, IP, IPA 64Mb 104 MHz / -- * I, IA, IP, IPA 256Mb 1 104 MHz / -- * I, IA 512Mb 1 133 MHz / 80 MHz * I, IA, IP, IPA 128Mb (FL129P) 104 MHz / -- * I, IA, IP, IPA 64-128Mb ≥256Mb 256Mb 1 133 MHz / 80 MHz * I, IA, IP, IPA 1Gb 1 133 MHz / 80 MHz * I, IA, IP, IPA 256Mb 133 MHz / 80 MHz * I, IA, IP, IPA 512Mb 133 MHz / 80 MHz * I, IA, IP, IPA 1Gb 1 133 MHz / 80 MHz * I, IA, IP, IPA 128Mb 133 MHz / 80 MHz * I, IA, IP, IPA Q215 64Mb 133 MHz / 100 MHz * I, IA, IP, IPA, E, EA Q116 256Mb 133 MHz / 80 MHz * I, IA, IP, IPA, E, EA 512Mb 133 MHz / 80 MHz * I, IA, IP, IPA 1Gb 1 133MHz / 80MHz * I, IA, IP, IPA 128Mb (FL128S) 133 MHz / 80 MHz * I, IA, IP, IPA, E, EA 128Mb (FL127S) 108 MHz / -- * I, IA, IP, IPA Q215 128Mb (FL128P) 104 MHz / -- * I, IA, IP, IPA ≤32Mb Density (Name) SDR / DDR * footnotes 256Mb 133 MHz / 66 MHz * I, IA, IP, IPA, E, EA Q316 128Mb 133 MHz / 66 MHz * I, IA, IP, IPA, E, EA Q316 64Mb Contact Sales 32Mb Contact Sales 256Mb 133 MHz / 66 MHz * I, IA, IP, IPA, E, EA Q116 128Mb 133 MHz / 66 MHz * I, IA, IP, IPA, E, EA Q116 64Mb 108 MHz / -- * I, IA, IP, IPA, E, EA 32Mb 108 MHz / -- * I, IA, IP, IPA, E, EA 16Mb 108 MHz / -- * I, IA, IP, IPA, E, EA 8Mb 76 MHz / -- * I 4Mb 85 MHz / -- * I 16Mb 65 MHz / -- * I Q116 DevelopmentConceptProductionSampling Status QQYY Availability EOL (Last-Time-Ship) *I = Industrial: −40ºC to +85ºC IA = Industrial, AEC-Q100: −40ºC to +85ºC IP = Industrial plus: −40ºC to +105ºC IPA = Industrial plus, AEC-Q100: −40ºC to +105ºC E = Extended: −40ºC to +125ºC EA = Extended, AEC-Q100: −40ºC to +125ºC 1 S70/S79 series (stacked die) QQYY Roadmap FL= 3.0 V FS= 1.8 V P,K= 90nm L,S= 65nm

11. 10 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Here’s How to Get Started 1. Download the datasheet: S25FL256SS25FL256S 2. Download our app note: Cypress FL-S SPI NOR Flash MemoryCypress FL-S SPI NOR Flash Memory 3. Register to access online technical supportRegister 4. Contact Cypress for more informationContact Set-top Box by Pace LTE Networking Device by D-Link Getting Started

12. 11 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) APPENDIX Appendix

13. 12 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Appendix Table Of Contents SlideTopicDescription 13References and LinksA list of links to key documents 14128Mb (FL127S) Product OverviewA product overview of the 128Mb part (SDR only) 15128Mb (FL128S) Product OverviewA product overview of the 128Mb part (SDR and DDR) 16512Mb Product OverviewA product overview of the 512Mb part 171Gb Product OverviewA product overview of the 1Gb part 18Part Selector GuideThe part number decoder for this NOR Flash Memory family 19128Mb Competitive Comparison Slide The combined FL127S/FL128S Competitive Comparison version for the 128Mb parts 20512MB Competitive Comparison SlideThe Competitive Comparison version for the 512Mb part 211Gb Competitive Comparison SlideThe Competitive Comparison version for the 1Gb part

14. 13 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) References and Links S25FL-S datasheets: Cypress 256Mb SPI NOR Flash Memory Cypress 128Mb SPI NOR Flash Memory (FL128S) Cypress 256Mb SPI NOR Flash MemoryCypress 128Mb SPI NOR Flash Memory (FL128S) Cypress 128Mb SPI NOR Flash Memory (FL127S) Cypress 512Mb SPI NOR Flash Memory Cypress 1Gb SPI NOR Flash Memory App notes: To educate yourself on SPI NOR Flash MemoryTo educate yourself on SPI NOR Flash Memory Website: Cypress FL-S NOR Flash Memory to learn moreCypress FL-S NOR Flash Memory to learn more Design models: IBIS and Verilog models to simplify your designIBIS and Verilog models to simplify your design Driver and software: To accelerate your design cycleTo accelerate your design cycle Cross reference guide: To see how Cypress stacks up with the competitionTo see how Cypress stacks up with the competition Cross reference tool: To easily replace the competitor’s SPI NOR Flash MemoryTo easily replace the competitor’s SPI NOR Flash Memory Hardware development tools: Kits, Cards, Boards to simplify designKits, Cards, Boards to simplify design Product selector guide: To choose the correct Cypress SPI productTo choose the correct Cypress SPI product References and Links

15. 14 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Sampling: Now Production:Now Cypress’s 128Mb (FL127S) Quad SPI NOR Flash Memory Printers Networking devices Set-top boxes Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 20-year data retention at +55°C SDR 4 clock rate: 108-MHz QIO 5 Program 1 time (256B): 0.395 ms (typical) Sector Erase 2 time (64KB): 130 ms (typical) Industrial temp range (AEC-Q100 opt.): -40°C to +85°C Industrial plus temp range (AEC-Q100 opt.): -40°C to +105°C Packages: 8-SOIC 208 mil, 16-SOIC 300 mil, 8-WSON 6 6 mm x 5 mm, 24-ball BGA 6 mm x 8 mm Features Datasheet: S25FL127S Download App Note: Cypress FL-S SPI NOR Flash MemoryS25FL127SCypress FL-S SPI NOR Flash Memory Collateral Block Diagram Availability 5 Quad input/output (QIO): An interface that transfers addresses or data on four I/O’s simultaneously 6 Very, Very Thin, Small-Outline, No-Lead semiconductor package 7 Signals used for standard Quad (x4) SPI interface. Refer to the S25FL127S datasheet for signalS25FL127S definitions in the x1 and x2 mode. 8 RESET# is an optional signal available on 16-SOIC and BGA packages. 9 Read data buffer Product Overview 128Mb (FL127S) Quad SPI NOR Flash Memory 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation required prior to a NOR Flash Memory Program, in which all the bits in a Sector are set to value “1” 3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it wears out 4 Single data rate: A mode of data transfer in which data is transferred once per clock cycle SRAM I/O Array Left Control Logic RD 9 Array Right Data Path X/Y Decoder CS# 7 SCK 7 IO0 7 IO1 7 IO3 7 IO2 7 RESET# 8

16. 15 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Sampling: Now Production:Now Cypress’s 128Mb (FL128S) Quad SPI NOR Flash Memory Advanced driver assistance systems (ADAS) Automotive instrument clusters Automotive infotainment systems White goods Set-top boxes Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 20-year data retention at +55°C SDR 4 clock rate: 104-MHz QIO 5 DDR 6 clock rate: 80-MHz QIO 5 Program 1 time (256B): 0.250 ms (typical) Sector Erase 2 time (64KB): 130 ms (typical) Industrial temp range (AEC-Q100 opt.): -40°C to +85°C Industrial plus temp range (AEC-Q100 opt.): -40°C to +105°C Extended temp range (AEC-Q100 opt.): -40°C to +125°C Packages: 16-SOIC 300 mil, 8-WSON 7 6 mm x 8 mm, 24-ball BGA 6 mm x 8 mm Features Datasheet: S25FL128S Download App Note: Cypress FL-S SPI NOR Flash MemoryS25FL128SCypress FL-S SPI NOR Flash Memory Collateral Block Diagram Availability 5 Quad input/output (QIO): An interface that transfers addresses or data on four I/O’s simultaneously 6 Double data rate: A mode of data transfer in which data is transferred twice per clock cycle 7 A thin, small-outline, no-lead semiconductor package 8 Signals used for standard Quad (x4) SPI interface. Refer to the S25FL128S datasheet for signalS25FL128S definitions in the x1 and x2 mode. 9 RESET# is an optional signal available on 16-SOIC and BGA packages. 10 Read data buffer Product Overview 128Mb (FL128S) Quad SPI NOR Flash Memory 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation required prior to a NOR Flash Memory Program, in which all the bits in a Sector are set to value “1” 3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it wears out 4 Single data rate: A mode of data transfer in which data is transferred once per clock cycle SRAM I/O Array Left Control Logic RD 10 Array Right Data Path X/Y Decoder CS# 8 SCK 8 IO0 8 IO1 8 IO3 8 IO2 8 RESET# 9

17. 16 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Sampling: Now Production:Now Cypress’s 512Mb (FL512S) Quad SPI NOR Flash Memory Advanced driver assistance systems (ADAS) Automotive instrument clusters Automotive infotainment systems Base stations Set-top boxes Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 20-year data retention at +55°C SDR 4 clock rate: 104-MHz QIO 5 DDR 6 clock rate: 80-MHz QIO 5 Program 1 time (512B): 0.340 ms (typical) Sector Erase 2 time (256KB): 520 ms (typical) Industrial temp range (AEC-Q100 opt.): -40°C to +85°C Industrial plus temp range (AEC-Q100 opt.): -40°C to +105°C Packages: 16-SOIC 300 mil, 24-ball BGA 6 mm x 8 mm Features Datasheet: S25FL512S Download App Note: Cypress FL-S SPI NOR Flash MemoryS25FL512SCypress FL-S SPI NOR Flash Memory Collateral Block Diagram Availability 5 Quad input/output (QIO):An interface that transfers addresses or data on four I/O’s simultaneously 6 Double data rate: A mode of data transfer in which data is transferred twice per clock cycle 7 Signals used for standard Quad (x4) SPI interface. Refer to the S25FL512S datasheet for signalS25FL512S definitions in the x1 and x2 mode. 8 RESET# is an optional signal available on 16-SOIC and BGA packages. 9 Read data buffer Product Overview 512Mb Quad SPI NOR Flash Memory 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation required prior to a NOR Flash Memory Program, in which all the bits in a Sector are set to value “1” 3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it wears out 4 Single data rate: A mode of data transfer in which data is transferred once per clock cycle SRAM I/O Array Left Control Logic RD 9 Array Right Data Path X/Y Decoder CS# 7 SCK 7 IO0 7 IO1 7 IO3 7 IO2 7 RESET# 8

18. 17 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Sampling: Now Production:Now Cypress’s 1Gb (FL01GS) Quad SPI NOR Flash Memory Advanced driver assistance systems (ADAS) Automotive instrument clusters Automotive infotainment systems Base stations Industrial controllers Applications Operating voltage range: 2.7 V to 3.6 V 100,000 Program 1 /Sector Erase 2 endurance cycles 3 20-year data retention at +55°C SDR 4 clock rate: 104-MHz QIO 5 DDR 6 clock rate: 80-MHz QIO 5 Program 1 time (512B): 0.340 ms (typical) Sector Erase 2 time (256KB): 520 ms (typical) Industrial temp range (AEC-Q100 opt.): -40°C to +85°C Industrial plus temp range (AEC-Q100 opt.): -40°C to +105°C Packages: 16-SOIC 300 mil, 24-ball BGA 6 mm x 8 mm Features Datasheet: S70FL01GS Download App Note: Cypress FL-S SPI NOR Flash MemoryS70FL01GSCypress FL-S SPI NOR Flash Memory Collateral Block Diagram Availability 5 Quad input/output (QIO):An interface that transfers addresses or data on four I/O’s simultaneously 6 Double data rate: A mode of data transfer in which data is transferred twice per clock cycle 7 Signals used for standard Quad (x4) SPI interface. Refer to the S70FL01GS datasheet for signalS70FL01GS definitions in the x1 and x2 mode. 8 RESET# is an optional signal available on 16-SOIC and BGA packages. 9 Read data buffer Product Overview 1Gb Quad SPI NOR Flash Memory CS1# 7 SCK 7 IO0 7 IO1 7 IO3 7 IO2 7 1 The operation required to change a value “1” to a value “0” in NOR Flash Memory 2 The operation required prior to a NOR Flash Memory Program, in which all the bits in a Sector are set to value “1” 3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it wears out 4 Single data rate: A mode of data transfer in which data is transferred once per clock cycle CS2# 7 RESET# 8 SRAM I/O Array Left Control Logic RD 9 Array Right Data Path X/Y Decoder

19. 18 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) Serial NOR Flash Memory Product Selector Guide Product Selector Guide SXXFLYYYS AG M F I 0 0 1 Feature Identifier: Options for HPLC 1 /EHPLC 2, RESET#, VIO, Security Package Type: M = SOIC, N = WSON (N/A 512S/01GS), B = BGA 6x8 Temp Range: I = Industrial (-40ºC to +85ºC), V = Industrial plus (-40ºC to +105ºC), N = Extended (-40ºC to 125ºC) Package Material: F = Lead (Pb)-free (for SOIC/WSON only) H = Low-Halogen, Lead (Pb)-free (for BGA only) Base MPN: XX = 25, YYY = 127/128 128Mb MirrorBit Serial Flash Memory XX = 25, YYY = 256 256Mb MirrorBit Serial Flash Memory XX = 25, YYY = 512 512Mb 65-nm MirrorBit Serial Flash Memory XX = 70, YYY = 01G 1Gb Dual Die Stack MirrorBit Serial Flash Memory Performance: AB/AG = 108/133-MHz Multi-I/O, DP/ DS = 66/ 80-MHz DDR (N/A 127S) Sector Type: 0 = 64Kb Sectors (N/A 512S/01G), 1 = 256KB Sectors Packing Type: 0 = Tray, 1 = Tube (for SOIC/WSON only), 3 = 13” Tape & Reel S25/70FL-S Part Numbering Decoder 1 High-Performance Latency Code; see datasheet for more details 2 Enhanced High-Performance Latency Code; see datasheet for more details

20. 19 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) FeatureS25FL128SS25FL127SN25Q128A13W25Q128FVMX25L12835F SPI Clock Rate (SDR) QIO 1 104 MHz108 MHz 104 MHz133 MHz Read SDR QIO 1 Bandwidth (max)54 MBps 2 52 MBps 2 67 MBps 2 SPI Clock Rate (DDR)80 MHzNot Supported Read DDR Bandwidth (max)80 MBps 3 Not Supported Program Time (256B) 4 0.25 ms0.395 ms0.50 ms0.70 ms0.50 ms Sector Erase Time (64KB) 4 130 ms 700 ms150 ms280 ms Chip Erase Time 4 33 s35 s170 s40 s50 s Temperature Range-40ºC to +125ºC-40ºC to +105ºC-40ºC to +125ºC-40ºC to +85 º C Packages SOIC16, WSON6x8, BGA SOIC8/16, WSON6x5, BGA Cypress 128Mb Quad SPI NOR Flash Memory vs. Competition’s Competitive Comparison 1 Quad input/output (QIO): An interface that transfers addresses or data on four I/O’s simultaneously 2 Calculated using SDR clock rate with QIO divided by two 3 Calculated using DDR clock rate with QIO 4 Conditions: 25ºC and V CC 3.0 V

21. 20 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) FeatureS25FL512SMT25QL512ABMX25L51245G SPI Clock Rate (SDR) with QIO 1 104 MHz133 MHz166 MHz Read SDR QIO 1 Bandwidth (max) 52 MBps 2 67 MBps 2 83 MBps 2 SPI Clock Rate (DDR) 80 MHz66 MHz100 MHz Read DDR Bandwidth (max) 80 MBps 3 67 MBps 3 100 MBps 3 Program Time (256B) 4 Not Supported0.20 ms0.25 ms Program Time (512B) 4 0.34 msNot Supported Sector Erase Time (64KB) 4 Not Supported150 ms280 ms Sector Erase Time (256KB) 4 520 msNot Supported Chip Erase Time 4 103 s153 s200 s Temperature Range -40ºC to +105ºC -40ºC to +85 º C Cypress 512Mb Quad SPI NOR Flash Memory vs. Competition’s Competitive Comparison 1 Quad input/output (QIO): An interface that transfers addresses or data on four I/O’s simultaneously 2 Calculated using SDR clock rate with QIO divided by two 3 Calculated using DDR clock rate with QIO 4 Conditions: 25ºC and V CC 3.0 V

22. 21 001-96821 Owner: ANSI/EWOO Rev *A Tech lead: NKUL 128Mb to 1Gb Quad SPI, FL-S NOR Flash Family NPI (Customer) FeatureS70FL01GSMT25QL01GBMX66L1G45G SPI Clock Rate (SDR) with QIO 1 104 MHz133 MHz Read SDR QIO 1 Bandwidth (max) 52 MBps 2 67 MBps 2 SPI Clock Rate (DDR) 80 MHz66 MHz83 MHz Read DDR Bandwidth (max) 80 MBps 3 66 MBps 3 83 MBps 3 Program Time (256B) 4 Not Supported0.20 ms0.25 ms Program Time (512B) 4 0.34 msNot Supported Sector Erase Time (64KB) 4 Not Supported150 ms280 ms Sector Erase Time (256KB) 4 520 msNot Supported Chip Erase Time 4 206 s306 s400 s Temperature Range -40ºC to +105ºC -40ºC to +85 º C Cypress 1Gb Quad SPI NOR Flash Memory vs. Competition’s Competitive Comparison 1 Quad input/output (QIO): An interface that transfers addresses or data on four I/O’s simultaneously 2 Calculated using SDR clock rate with QIO divided by two 3 Calculated using DDR clock rate with QIO 4 Conditions: 25ºC and V CC 3.0 V