Download presentation
Presentation is loading. Please wait.
1
The NFET explained… in only a few confusing slides.
2
Voltage-controlled Current Source g s d I DS = k ( ) ( V gs - V t ) W L 2 Drain Source Gate I DS V gs V ds Vds > Vgs-Vt Saturation Region: (1 + V ds ) Early Effect << 1
3
Fig 4-13 VtVt I ds V gs Drain Source Gate I DS V gs V ds Vds > Vgs - Vt
4
Ohmic (Triode) Region: I DS = k ( ) [ 2 (V gs - V t ) V ds - V ds ] W L 2 Vds < Vgs - Vt Drain Source Gate I DS (Vds is small)
![Ohmic (Triode) Region: I DS = k ( ) [ 2 (V gs - V t ) V ds - V ds ] W L 2 Vds < Vgs - Vt Drain Source Gate I DS (Vds is small)](http://images.slideplayer.com./39/10962306/slides/slide_4.jpg "Ohmic (Triode) Region: I DS = k ( ) [ 2 (V gs - V t ) V ds - V ds ] W L 2 Vds < Vgs - Vt Drain Source Gate I DS (Vds is small)")
5
V ds I ds Fig 4-12 Drain Source Gate I DS dotted line is what the previous graph plotted.
6
n+ p-type source = 0.0 vdrain = 0.0 v gate = 0.0 v NFET - Operation depletion regions
7
NFET - Operation n+ p-type source = 0.0 vdrain = 0.0 v gate = 0.0 v (subthreshold)
8
NFET - Operation n+ p-type source = 0.0 vdrain = 0.0 v gate = 0.4 v depletion region (subthreshold)
9
NFET - Operation n+ p-type source = 0.0 vdrain = 0.0 v gate = 0.6 v (subthreshold)
10
NFET - Operation n+ p-type source = 0.0 vdrain = 0.0 v gate = 0.75 v inversion A channel is formed…. Threshold Voltage, Vgs = 0.75 v
11
NFET - Operation n+ p-type source = 0.0 vdrain = 0.0 v gate = 1.0 v (above threshold) Ids = 0.0 A
12
NFET - Operation n+ p-type source = 0.0 vdrain =.05 v gate = 1.0 v (above threshold) Ids = 10 uA
13
NFET - Operation n+ p-type source = 0.0 vdrain = 0.1 v gate = 1.0 v (above threshold) Ids = 20 uA 0.1v0.05v
14
NFET - Operation n+ p-type source = 0.0 vdrain = 0.2 v gate = 1.0 v (above threshold) Ids = 40 uA 0.1v 0.2v.05v
15
NFET - Operation n+ p-type source = 0.0 vdrain = 0.25 v gate = 1.0 v (above threshold) Ids = 59 uA.05v0.1v 0.25v Pinch-off Vds > Vgs - Vt
16
NFET - Operation n+ p-type source = 0.0 vdrain = 0.3 v gate = 1.0 v (above threshold) Ids = 60 uA.05v0.1v 0.25v Vds > Vgs - Vt
17
NFET - Operation n+ p-type source = 0.0 vdrain = 0.4 v gate = 1.0 v (above threshold) Ids = 61 uA.05v0.1v 0.25v Vds > Vgs - Vt = Vgs-Vt
18
NOTICE - the saturation region is now up where the current is constant for different V DS. V ds I ds Fig 4-12 the arrows indicate what we showed in the previous figures as Vds was increased for a fixed Vgs
Similar presentations
![EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]](/16/5062541/big_thumb.jpg "EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]>")
