1. GGT-Electronics System design Alexander Kluge CERN-PH/ED April 3, 2006

2. A. Kluge General: Chip Specifications Chip Parameter SpecificationPreliminary Design parameter Time resolution 160/200 ps160/200 ps (bin size?) Beam size (a x b) 48 x 36 mm 2 Pixel size (a x b) 300 x 300 µm 2 Matrix size (a x b) 32 x ? Active area/per chip (a x b) 9.6 x ? mm 2 # chip/module (a x b) 5 x 2 / 5 x 3 / 4 x 3 Calculation,simulationWorking parameters

3. April 3, 2006A. Kluge General: Chip Specifications Chip Parameter First ideasSpecificationPreliminary Design parameter Avg Rate: avg/max 60/173 MHz/cm 2 Depends on TDC, segmentation Efficiency99% 98% for center?? Number of pixels/segment 1 (analog TDC) 7-20 (digital TDC) Dead time of segment 100 ns for 1 TDC/pixel 7 -10 ns for shared TDC Buffer size per segment Readout speed/Trans- mission speed Needs to operate in vacuum Yes/no ??

4. April 3, 2006A. Kluge inputsoutput I/O block diagram of chip

5. April 3, 2006A. Kluge I/O of chip Which connections to on-detector electronics? –2 Power supplies per chip: Core supply; analog and digital (1.5V / 1.3A / 2W) I/O supply (≤ 2.5V / ~0.1A) Several wire pads (~30) but all to few conductors outside –Outputs (5 Gbits/s) Data: ≥ 2 high speed serial outputs (differential 3 Gbit/s) Status: 1 low speed serial output pair (6 pads) –Inputs Clock input: 1 differential pair Configuration & control: 1 low speed serial output pair 2 single ended control 8 config (6 + 8 pads)

6. April 3, 2006A. Kluge clk 2 2 control data0 2 2 data1 status 2 10 test config 8 control 2 5VddCoreAna 5GndCoreAna5 GndIO 5 VddCoreDig 5 VddIO 5 GndCoreDig 2 2 2 111 1 2 2 2 I/O block diagram of chip

7. April 3, 2006A. Kluge Configuration

8. April 3, 2006A. Kluge Chip size Readout and supply 21 mm18 mm 3 mm Readout needs possibly more space -> not leaving 18mm active area Supply from one side has strong power drop Thinning of long narrow chips more difficult Readout and supply

9. April 3, 2006A. Kluge Configuration Highest rate

10. April 3, 2006A. Kluge Configuration Max rate on one chip, but chip smaller

11. April 3, 2006A. Kluge Configuration: study starting point

12. April 3, 2006A. Kluge Components in beam of 48 x 36 mm Si; 48 x 12 mm 2 ; 200 µm Si; 9.6 x (12+6) mm 2 ; 100 µm Carbon; 48 x 36 mm 2 ; 100 µm 48 x 9 mm 2 ; Al; 50 µm Kapton; 50 µm + 12 µm Al; 10 µm * 50% Al bonds; 2mm; 25 µm SMD comp 0402 (glued or wire bonded); 1 x 0,5 x 0.5 mm 3

13. April 3, 2006A. Kluge 9 mm Low mass cable

14. April 3, 2006A. Kluge Configuration Center: 0.45% X 0 Off Center1: 0.55% X 0 Off Center2: 0.65% X 0 Border: 0.65% X 0 Sensor&bonds: 0.24% X 0 RO chip: 0.11% X 0 Low mass cable: 0.10% X 0 Structure: 0.10% X 0 6 mm: 0.48% 3 mm: 0.58% 3 mm: 0.69% 3 mm: 0.58% 3 mm: 0.69% 9 mm: 0.69%

15. April 3, 2006A. Kluge Configuration: study starting point

16. April 3, 2006A. Kluge Signal lines 100µm width 200µm pitch + separation => ~ 0.7 mm per signal line Vdd lines 1mm & separation => ~1.2 mm Per chip and side: 3 Vdd + 3 signal => 5.7 mm 9 mm

17. April 3, 2006A. Kluge Configuration Sensor&bonds: 0.24% X 0 RO chip: 0.11% X 0 Low mass cable: 0.10% X 0 Structure: 0.10% X 0

18. April 3, 2006A. Kluge Conclusion: configuration What is the required material budget? Is the starting point configuration acceptable and if not what are the reasons? –Use reasons to adapt other parameters accordingly - geometric efficiency (areas of complete inefficiency), electronics efficiency, beam geometry

19. April 3, 2006A. Kluge Number of components needed 3 stations each consisting of: 1 module & mechanics & cooling 1 modules consists of: 3 assemblies 9 assemblies needed for GGT 100 days of operation: –Life time of assembly : 14 to 28 days => 4 to 7 exchange cycles 36 to 63 assemblies needed –in this scheme 4 low mass cables are needed for 1 module => in total 48 to 84 low mass cables needed

20. April 3, 2006A. Kluge

21. April 3, 2006A. Kluge Configuration 3 x 5 Assume matrix of 40 rows x 32 columns: –12 mm x 9.6 mm = 115.2 mm 2 Chip size –(12 + (2 x 3mm)) x 9.6 mm = 18 x 9.6 mm Pixel size 300 um x 300 um –=> 40 x 32 pixels = 1280 pixels Max. Avg Rate of column in center chip: ~150 MHz/cm 2 (for beam with max. 173 MHZ/cm 2 ) –=> 135 kHz/pixel –=> 173 MHz/chip –=> 173 MHz/chip * ~32 bit = 5.5 Gbit/s

22. April 3, 2006A. Kluge Configuration 3 x 4 Assume matrix of 40 rows x 40 columns: –12 mm x 12 mm = 144 mm 2 Chip size –(12 + (2 x 3mm)) x 12 mm = 18 x 12 mm Pixel size 300 um x 300 um –=> 40 x 40 pixels = 1600 pixels Max. Avg Rate of center chip: ~150 MHz/cm 2 (for beam with max. 173 MHZ/cm 2 ) –=> 135 kHz/pixel –=> 216 MHz/chip –=> 216 MHz/chip * ~32 bit = 6.9 Gbit/s

23. April 3, 2006A. Kluge Rate and super pixels Super pixel structure for rate maximum in center Column of 40 pixels 12 mm column centered on beam ~150 MHz/cm2 => 135 kHz/pixel => 99%, Td = 10ns, N=7, Nseg = 183; Td = 6 ns, N= 12, Nseg = 107; Td = 7.4 ns, N= 10, Nseg = 128; Readout and supply

24. April 3, 2006A. Kluge Rate and super pixels Super pixel structure for rate maximum in center Column of 40 pixels 12 mm column centered on beam ~150 MHz/cm2 => 135 kHz/pixel => 98%, Td = 10ns, N=14, Nseg = 91; Td = 6 ns, N= 24, Nseg = 53; Td = 7.4 ns, N= 20, Nseg = 64; Readout and supply

25. April 3, 2006A. Kluge Read out 3 planes x 3 x 5 chips x (2 high speed + 2 low speed + 1 clock) optical links = 90 high speed links + 90 low speed links+ 45 clock links

26. April 3, 2006A. Kluge ALICE pixel trigger processor BRAIN HS0 HS1 HS11 HS108 HS109 HS119 12 x 800 MHz JTAG parallel bus DDL Ethernet Multi Gigabit serial link DAQ data link control & data to computer (control room) CTP clk SPD RO TTC Multi Gigabit serial link JTAG parallel bus OPTIN9 FPGA config Multi Gigabit serial link JTAG Control serial link parallel bus OPTIN0 FPGA config Control serial link Parallel data bus TTC

27. April 3, 2006A. Kluge Conclusion Configuration specification have influence on chip and system design Full information and choice of options only during design of full chip