1. μComputer Structure μProcessor Memory Bus System I/O Ports

2. PPI (INTEL) 8255, PIA (MOTOROLA) 6821 I Port O Port Thermocouple Amplifier AD Converter Temperature mV V Word DA Converter Driving Circuit Valve Word V Hydraulic or Electric Signal Flow Control

3. Memory memory address content FFFFF H 00000 H 00001 H 00002 H F1 H 29 H D5 H 00 H 23 H 78 H Address Space 8 bits20 bits Volatile: RAMs (R,W) Non-volatile: ROM, PROM, EPROM, EEROM

4. The μProcessor The 8086 or 8088 μP Available in 40 Pins DIP Performs arithmetic and logical operations Decodes program instructions Controls the μComputer operation Contains some memory μP = CPU

5. The System Bus Address Bus Data Bus Control Bus The address bus contains 16 unidirectional lines The data bus contains 8 bidirectional lines The control bus is made of individual lines that are unidirectional in most of the cases, but sometimes are bidirectional

6. Program Execution μPμPmemory Address Bus Data Bus Program counter Address decoder Instructions & data Instruction register Instruction decoder 1 23 4 5 6 7 8

7. μP History 19738-bit Word8080INTEL 19744-bit Word4040INTEL 19744-bit WordTMS1000Texas Instruments 19748-bit WordF8Fairchild 19748-bit Word6800MOTOROLA 19758-bit Word6502COMMODORE 19768-bit Word8085ÌNTEL 19768-bit WordZ80ZILOG 197816-bit Word8086INTEL 198016-bit Word8088INTEL 198016-bit Word68000MOTOROLA

8. Introduction to μP Microprocessors and Peripherals Brey Merrill ISBN: 0-675-20884-X

9. How A 16 bit word is stored in 2 consecutive 8 bit memory locations ABCD H 00724 H 00725 H CD H AB H

10. Software Model of the 8086 or 8088 μP 8086 or 8088 μP AH BH CH DH AL BL CL DL Data Registers Segment Registers CS DS SS ES Index Registers SI DI Pointer Registers SP BP IP Instruction Pointer SR Status register 9 bits AX BX CX DX

11. XXXX0 H Memory Segmentation CS DS SS ES Code Segment Data Segment Stack Segment Extra Segment 00000 H FFFFF H 64KB XXXX0 H Physical Address

12. Dedicated and General Use of Memory 0H0H 7F H 80 H FFFEF H FFFFF H 128 Bytes to store pointers to interrupt service routines Each pointer requires 4 memory locations Open memory reserved 12 Bytes

13. Physical &Logical Addresses 02800 H 02801 H 02802 H 02803 H 02804 H 02805 H 02806 H 02807 H 02808 H 02809 H 0280A H 0280B H Physical Address Segment Base Offset 000B H Logical Address 0280 H :000B H 0280B H

14. Address of the next instruction to be executed Instruction Pointer 1234 H + Code Segment 8888 H Physical address 89AB4 H Logical address 8888 H :1234 H 88880 H +1234 H = 89AB4 H General purpose registers AX BX CX DX Accumulator register Base register Count register Data register

15. Pointer & Index Registers SP BP Stack pointer Base pointer SS:SP points to the top of the stack The top of the stack is the next stack location that can accessed SS:BP is used in the based addressing mode SS:BP can be used to examine the values of the parameters passed to a subroutine and held in the stack SI DI Source index Destination index DS:SI DS:DI Indexed type of addressing For indexing source or destination addresses

16. Status Register CFPFAFZFSFOFIFDFTF Control flagsStatus flags carry parity auxiliary carry zero sign overflow trap direction Interrupt enable CY, NC