1. EECE 320 L8: Combinational Logic design Principles 1Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 8: Combinational Logic Design Principles Ali Chehab

2. EECE 320 L8: Combinational Logic design Principles 2Chehab, AUB, 2003 Timing Hazards  So far we have ignored circuit delays in our steady-state analysis.  Because of circuit delays, the transient behavior of a circuit may be different than its steady-state behavior.  A hazard exists when it is possible for the circuit to produce a glitch (short pulse) that is un-accounted for in steady-state analysis causing a temporary false output l Static hazards: Static-1 and Static-0 hazards l Dynamic hazards  A static hazard is a condition where a single variable change produces a momentary output change when no output change should occur. 1 0 Static-1 hazard 1 0 Static-0 hazard  A dynamic hazard is a condition where the output changes three or more times when it should change from 1 to 0 or 0 to 1 only, due to the presence multiple paths from input to output with different delays. 1 0 Dynamic hazard

3. EECE 320 L8: Combinational Logic design Principles 3Chehab, AUB, 2003 Timing Hazards  Consider the following AND-OR circuit:  Pair of XYZ inputs with one variable changing: XYZ: 111 --> 110 l Output changes to 0 momentarily because of the delay through the inverter when it is supposed to remain 1 1 1010 1 101101

4. EECE 320 L8: Combinational Logic design Principles 4Chehab, AUB, 2003 Timing Hazards  Consider the following OR-AND circuit:  Pair of WXYZ inputs with one variable changing: WXYZ: 0000 --> 0001 l Output changes to 1 momentarily because of the delay through the inverter when it is supposed to remain 0.

5. EECE 320 L8: Combinational Logic design Principles 5Chehab, AUB, 2003 Timing Hazards  In general, in 2-level implementations, we must add consensus terms (redundant gates) to eliminate hazards.

6. EECE 320 L8: Combinational Logic design Principles 6Chehab, AUB, 2003 Timing Hazards  Example of eliminating static-1 hazards

7. EECE 320 L8: Combinational Logic design Principles 7Chehab, AUB, 2003 Hardware Description Language (HDL)  An HDL is a language that describes the hardware of digital systems in a textual form. l Similar to a programming language, but more oriented towards hardware  We can use an HDL to represent/describe logic diagrams, Boolean expressions, combinational circuits, sequential circuits, even a complete microprocessor.  Applications of HDLs: l Logic design: Describe/model the design of a digital system l Logic simulation: Simulate the behavior of a digital system l Logic synthesis: Derive a list of components (gates) and their interconnections (netlist) from the model of a digital system described in HDL, ready for hardware implementation.  The computer-aided design process using an HDL is called design flow  Two standard HDLs: l VHDL (mid 80’s): We will use in EECE 320 l Verilog HDL (1984): Once you learn VHDL, it is easy to learn Verilog

8. EECE 320 L8: Combinational Logic design Principles 8Chehab, AUB, 2003 The VHDL Language  Launched by U.S. DoD and IEEE in mid 80’s as part of the VHSIC program  Original intention for documentation & modeling  Became popular after the introduction of synthesis tools l Create logic circuits from behavioral description ready for fabrication  Standardized by IEEE in 1987 and extended in 1993 l VHDL-87, VHDL-93  Features: l Designs may be decomposed hierarchically each consisting of design elements l A design element has an interface and a behavioral specification (simulation) l A behavioral spec uses an algorithm or a hardware structure to define an element’s operation. l The logical operation and timing behavior of a design can be simulated. V HDL VHSIC Very High Speed Integrated Circuit

9. EECE 320 L8: Combinational Logic design Principles 9Chehab, AUB, 2003 HDL-Based Design Flow Design Entry High-level Analysis Technology Mapping Low-level Analysis Library EECE 320

10. EECE 320 L8: Combinational Logic design Principles 10Chehab, AUB, 2003 HDL-Based Design Flow: Design Entry Design Entry  A design can be described and represented: l Textually using an HDL (e.g. VHDL text editor), or l Graphically using schematics (schematic editor)  Compilation: The design is then compiled and checked for syntax errors (VHDL compiler).  Result of design specification and compilation is called a Netlist (Network List) consisting of: l Generic primitives - Logic gates, flip-flops, … l Technology specific primitives - Transistors l Higher level library elements - adders, ALUs, decoders, …  Example: Netlist of a schematic design g1 g2 g3 n1 n2 n3 n4 n5 n6 n7 g1 “and” n1 n2 n5 g2 “and” n3 n4 n6 g3 “nand” n5 n6 n7 High-level Analysis Technology Mapping Low-level Analysis

11. EECE 320 L8: Combinational Logic design Principles 11Chehab, AUB, 2003 Example of a Schematic Capture Design Entry

12. EECE 320 L8: Combinational Logic design Principles 12Chehab, AUB, 2003 Example of a VHDL Design Entry

13. EECE 320 L8: Combinational Logic design Principles 13Chehab, AUB, 2003 HDL-Based Design Flow: High Level Analysis High-level Analysis  High-level analysis is used to: l Optimize the design l Verify functionality (functional verification) l Obtain rough estimates of timing, power, and cost  Commonly used tools: l Logic simulator: To check functional correctness l Static timing analyzer: To estimate circuit delays based on timing models and delay parameters for library elements. Design Entry Technology Mapping Low-level Analysis

14. EECE 320 L8: Combinational Logic design Principles 14Chehab, AUB, 2003 Technology Mapping & Low-Level Analysis Technology Mapping Low-level Analysis Design Entry High-level Analysis  Mapping the analyzed design into a specific technology (technology library)  Converts the netlist into elements supported by the technology l EX: Maps design elements into library elements  Performs l Partitioning of the design l Placement of design elements l Routing wires between design elements … so as to meet certain performance specs.  Low-Level Analysis l Simulation and analysis tools perform level checks with accurate timing models, accurate wire delays, accurate power models, …  Obtain more accurate estimates about the performance of the design before fabrication

15. EECE 320 L8: Combinational Logic design Principles 15Chehab, AUB, 2003 Example: Design Obtained After Technology Mapping

16. EECE 320 L8: Combinational Logic design Principles 16Chehab, AUB, 2003 VHDL Program Structure

17. EECE 320 L8: Combinational Logic design Principles 17Chehab, AUB, 2003 VHDL Program File Structure -- First VHDL Program entity Inhibit is -- aka ‘BUT-NOT port (X, Y: IN BIT; Z : OUT BIT); End Inhibit; architecture behave of Inhibit is begin Z <= ‘1’ when X = ‘1’ and Y = ‘0’ else ‘0’; end behave;

18. EECE 320 L8: Combinational Logic design Principles 18Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders