1. MAPLD 2005/213Kakarla & Katkoori Partial Evaluation Based Redundancy for SEU Mitigation in Combinational Circuits MAPLD 2005 Sujana Kakarla Srinivas Katkoori {kakarla, katkoori}@cse.usf.edu Computer Science & Engineering University of South Florida

2. MAPLD 2005/213Kakarla & Katkoori 2 Outline of The Presentation  Introduction Radiation Effects and SEUs  State-of-the-art SEU Detection and Mitigation Techniques  Introduction to the Proposed Technique Partial Evaluation Temporal Triple Modular Redundancy  Proposed Technique Partial Evaluation Based TMR  Experimental Results  Conclusions

3. MAPLD 2005/213Kakarla & Katkoori 3 Radiation Effects  Long Term Ionizing Radiation Effects (total dose)  Transient Ionizing Radiation Effects (dose rate)  Single Event Effects Single Event Upset (SEU) Single Event Transient (SET) Single Event Latchup (SEL) Single Event Functional Interrupt (SEFI) Single Event Gate Rupture (SEGR) Single Event Burnout (SEB)  Displacement Damage

4. MAPLD 2005/213Kakarla & Katkoori 4 N+ P Substrate SourceDrain Gate MOS Transistor Highly charged particle Oxide Insulation - - - - - - - - - - - - - - - - - + + + + + + - - - - - - - - - - - - - - - - - + + + + + + SEU Mechanism

5. MAPLD 2005/213Kakarla & Katkoori 5 Radiation Hardening Radiation hardening: Protection to chips to make them more resistant to ionizing radiation. Radiation hardened protective package Process hardness Design or layout techniques

6. MAPLD 2005/213Kakarla & Katkoori 6 Radiation Hardening Contd.,  Radiation Hardening by Protective Package Shielding the circuits  Radiation Hardening by Fabrication Change in the method of manufacturing transistors in the circuit Isolating a device from surrounding components

7. MAPLD 2005/213Kakarla & Katkoori 7 Radiation Hardening by Design  System level design hardening Coding techniques Current monitoring techniques  Circuit and Logic design Storage latch duplication State-restoring feedback circuits Transistor sizing  Redundancy Lockstep system Triple Modular Redundancy Dual voting double redundancy Selective Triple Modular Redundancy

8. MAPLD 2005/213Kakarla & Katkoori 8 Partial Evaluation Widely used in the software applications Not popular in hardware because of its static nature Optimization by exploiting prior knowledge Functional level Partial Evaluation Propagate known values throughout the function Obtain new specialized function Done at run time Techniques : Symbolic computation, Loop unrolling, Memoization, etc., Advantages: Speed up Efficient and modular solution

9. MAPLD 2005/213Kakarla & Katkoori 9 Circuit Delay Unit Delay Unit Voter circuit Temporal TMR Transient pulse with low pulse width No change in the value of bit Delay caused by the delay unit Transient pulse

10. MAPLD 2005/213Kakarla & Katkoori 10 Circuit Delay Unit Delay Unit Voter circuit Temporal TMR Delay caused by the delay unit Transient pulse with high pulse width Value of the bit is flipped

11. MAPLD 2005/213Kakarla & Katkoori 11 Partial Evaluation Based Triple Modular Redundancy  Observation If some input values are known in advance The entire circuit need not be triplicated Gates with constant output can be eliminated Functionally equivalent reduced circuit is obtained T riplicate the reduced circuit

12. MAPLD 2005/213Kakarla & Katkoori 12 Need for Temporal TMR Temporal TMR is used in cases when the actual inputs to the circuit are not in accordance with the rounded values A = 0.124 B = 0.46 C = 0.84 0 B = 0.46 C = 0.84 A = 0 B = 1 C = 0 Out = 0 0 0.3864 A = 1 B = 1 C = 0 Out = 1 A = 0 B = 1 C = 0 Out = 0 A = 1 B = 1 C = 0 Out = 0

13. MAPLD 2005/213Kakarla & Katkoori 13 Definitions Redundant gate: A gate is said to be redundant if its output can be determined in advance based on the knowledge of its inputs. Rounding the input probabilities: Suppose the input probability p is such that 0.0 ≤ p ≤ 0.2, logic value = 0 0.9 ≤ p ≤ 1.0, logic value = 1

14. MAPLD 2005/213Kakarla & Katkoori 14 Rounding probabilities Propagate probabilities Resolve logic on signals Obtain functionally equivalent reduced circuit Determine output from Partially evaluated circuit Determine output from Temporal TMR circuit Selection of output from the two sets of values Validation Partial Evaluation TMR Flow Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7

15. MAPLD 2005/213Kakarla & Katkoori 15 Step 1: Rounding the probabilities If the input probabilities are such that 0.0 ≤ p ≤ 0.2 => logic value = ‘0’ 0.9 ≤ p ≤ 1.0 => logic value = ‘1’ The rounded probability values are then propagated over the circuit

16. MAPLD 2005/213Kakarla & Katkoori 16 Step 2: Propagate Probabilities Type of GateOutput probability AND NAND OR NOR XOR XNOR

17. MAPLD 2005/213Kakarla & Katkoori 17 Step 3: Redundant gate elimination All redundant gates are eliminated “not” gate cannot be eliminated Gates in the last level cannot be eliminated

18. MAPLD 2005/213Kakarla & Katkoori 18 Step 4: TMR Insertion The reduced circuit is duplicated A majority voter is used at each output Original Circuit Reduced Circuit Reduced Circuit Majority Voter Circuit Correct output

19. MAPLD 2005/213Kakarla & Katkoori 19 Step 5: Temporal TMR For temporal TMR, pass each of the output through a series of two delay units We now have the output determined at three instances of time A majority voter is used to determine the correct output Original Circuit Majority Voter Circuit Delay unit Correct output

20. MAPLD 2005/213Kakarla & Katkoori 20 Step 6: Output Selection Two sets of output values, one set from partial evaluation based TMR the other from Temporal TMR Multiplexer selects the correct output among the two sets Suppose probability of input A, p is such that 0.9 ≤ p ≤ 1.0 probability of input B, q is such that 0.1 ≤ q ≤ 0.2 then the select line for the multiplexer is Ā + B

21. MAPLD 2005/213Kakarla & Katkoori 21 Original circuit Reduced circuit Reduced circuit Majority voter circuit for T-TMR Majority voter circuit for PE Logic for select line of multiplexer delay unit Final output select line

22. MAPLD 2005/213Kakarla & Katkoori 22 Step 7: Validation Faults representing SEUs are introduced into the circuit using a SEU simulator Faulted circuit is functionally verified using NC Cadence Launch Outputs of the original circuit without faults and outputs of the faulted circuit are compared to check if any fault has propagated to the output Original circuit SEU Simulator Implementation of partial evaluation Comparison Results Reduced circuit Simulate faulted circuit Simulate original circuit

23. MAPLD 2005/213Kakarla & Katkoori 23 Advantages and Disadvantages of Partial Evaluation based TMR  Advantages Less area overhead Power savings High tolerance to SEUs  Disadvantages In the worst case, area overhead is greater than the full TMR Delay overhead when Temporal TMR is used Spatial TMR Area overhead Temporal TMR Delay overhead PE based TMR

24. MAPLD 2005/213Kakarla & Katkoori 24 Experimental Results Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) X37064029956.946.9 Cm150a5841170.634.26 Alu2335207561.934.04 9symml16692155.4232.47 alu467437165532.25 Count1056215931.66 Too_large674342350.7431.5

25. MAPLD 2005/213Kakarla & Katkoori 25 Experimental Results Contd., Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) I216184152.1730.18 Mux7941153.1626.14 C432209108451.624.19 Frg1100583 23.39 Cordic6438259.321.1 term1364167945.8720.83 I415482653.2418.1 I310666662.2616.37

26. MAPLD 2005/213Kakarla & Katkoori 26 Experimental Results Contd., Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) F51m12373759.314.86 Vda805403395013.4 Cmb4329467.4412.4 C8803171972462.7311.46 C26706773143446.3811.25 Z4ml5236469.2310.46 Cm85a3222368.7510.18 Cm151a2920168.99.8

27. MAPLD 2005/213Kakarla & Katkoori 27 Experimental Results Contd., Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) Cm152a2313156.529.5 I97574706352.089.3 X13072032866.128.77 C19083981902547.77.3 Parity159160.56.1 Ttt22041332165.193.5 My_adder1461001768.490.59

28. MAPLD 2005/213Kakarla & Katkoori 28 Experimental Results Contd., Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) *c8162981762.3-0.1 *cm162a4431570.45-0.6 *cm163a4332569.76-3.3 *i75522366743.11-14.1 *x44392246551.02-17.5

29. MAPLD 2005/213Kakarla & Katkoori 29 Conclusions Greater savings in area are obtained for circuits with more number of gates less number of outputs The area overhead for the technique decreases with the number of outputs Area overhead of PTMR circuit is less than TMR but has greater delay overhead Delay overhead of PTMR is less than Temporal TMR