1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and Contest Results of Phase René Romann

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Overview Slide 2 1.Analyzing the Metric 2.Optimizing the Metric 3.Different Speeds 4.Results of own Design 5.Goals for next term

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 1. Analyzing the Metric Slide 3

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 2. Optimizing the Metric Slide 4 Reducing the Metric due to: Optimized Gate count [different logic] Trying to find optimal speed Reducing overall Area of Gates

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 2. Optimizing the Metric Slide 5 Optimize Gate count Using small parts Reuse as many parts as possible [term sharing]

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 2. Optimizing the Metric Slide 6 Optimal Speed Speed depends on voltage No linear scaling

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 2. Optimizing the Metric Slide 7 Reduced Overall Gate Area: Depends on Logic Less logic needs less gates Depends on Speed Higher speed needs bigger gates

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 3. Different Speeds Slide 8 Different speeds 100 MHz – Metric around 8 * 10 -12 250 MHz – Metric around 3.7 * 10 -12 500 MHz – Metric around 2.74 * 10 -12 1 GHz – Metric around 3.3 * 10 -12  Nonsense to increase speed any further

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 4. Results of own implementation Mandatory values for ASIC (Ex.) Frequency f500,00 MHz Area A24 721 μm² Power P leak 2.1218 μW Operation time t OP 82.75 μs E avg 0.2499433 Metric2.74155 * 10 -12 Ws

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 5. Goals for next term Slide 10 Decrease Leakage power Increase Speed Reduce Area [e.g. use other adders?]