1. L26 April 261 EE5342 – Semiconductor Device Modeling and Characterization Lecture 26 - Spring 2005 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

2. L26 April 262 MOSFET Device Structre Fig. 4-1, M&A*

3. L26 April 263 n-channel enhancement MOSFET in ohmic region 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat e - e - e - e - e - n+ p-substrate Channel

4. L26 April 264 Basic I-V relation for MOS channel

5. L26 April 265 Universal drain characteristic 9I D1 IDID 4I D1 I D1 V GS =V T +1V V GS =V T +2V V GS =V T +3V V DS saturated, V DS >V GS -V T ohmic

6. L26 April 266 MOSFET equivalent circuit elements Fig 10.51*

7. L26 April 267 n-channel enh. circuit model G D B S C gs C gd C gb C bs C bd RD RG RB RDS Idrain D SS D SD

8. L26 April 268 MOS small-signal equivalent circuit Fig 10.52*

9. L26 April 269 MOSFET circuit parameters

10. L26 April 2610 MOSFET circuit parameters (cont)

11. L26 April 2611 Substrate bias effect on V T (body-effect)

12. L26 April 2612 Body effect data Fig 9.9**

13. L26 April 2613 Fully biased n- channel V T calc

14. L26 April 2614 Values for  ms with silicon gate

15. L26 April 2615 Q’ d,max and x d,max for biased MOS capacitor Fig 8.11** x d,max (microns) |Q’ d,max |/q (cm -2 )

16. L26 April 2616 I-V relation for n-MOS IDID V DS V DS,sat I D,sat ohmic non-physical saturated

17. L26 April 2617 MOS channel- length modulation Fig 11.5*

18. L26 April 2618 Analysis of channel length modulation

19. L26 April 2619 Channel length mod- ulated drain char Fig 11.6*

20. L26 April 2620 Associating the output conductance IDID V DS V DS,sat I D,sat

21. L26 April 2621 SPICE mosfet Model Instance CARM*, Ch. 4, p. 290 L = Ch. L. [m] W = Ch. W. [m] AD = Drain A [m 2 ] AS = Source A[m 2 ] NRD, NRS = D and S diff in squares M = device multiplier

22. L26 April 2622 SPICE mosfet model levels Level 1 is the Schichman-Hodges model Level 2 is a geometry-based, analytical model Level 3 is a semi-empirical, short- channel model Level 4 is the BSIM1 model Level 5 is the BSIM2 model, etc.

23. L26 April 2623 SPICE Parameters Level 1 - 3 (Static)

24. L26 April 2624 SPICE Parameters Level 1 - 3 (Static) * 0 = aluminum gate, 1 = silicon gate opposite substrate type, -1 = silicon gate same as substrate.

25. L26 April 2625 SPICE Parameters Level 1 - 3 (Q & N)

26. L26 April 2626 References CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995. M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997