1. Barcelona Group Clermont Ferrand 11/12/2003 FunctionsFunctions Boards location and distributionBoards location and distribution CB block diagram CB block diagram LVDS conversion LVDS conversion Needed signals from SPECS slaveNeeded signals from SPECS slave SPD multiplicity SPD multiplicity QuestionsQuestions SPD control board (CB)

2. SPD CB functions Configure/obtain data from/to the VFE board. Program Clock Distribution Chips (CDC) in order to supply the delayed clock to the VFE. SPD multiplicity.

3. Boards location and distribution There are 8 crates (4+4) with 2 slots avalaible for SPD CB in each crate: 16 CB. Every CB must be in charge of 6,25 VFE boards (100/16). –12 CB will be in charge of 7 VFE: 84.(crates 1,3 and 4) –4 CB will be in charge of 4 VFE: 16.(crate 2) –84+16=100 VFE. (see next pictures)

4. Boards location and distribution Crates 4 45836791011121314 SPD control 2 15 : SPD control Boards 7 8

5. Boards location and distribution Every CB will control the same SPD VFEs corresponding to PreShower neighbour cards assignation. Some control boards will control 4 VFE (crate 2) and some control boards will control 7 VFE (crates 1,3 and 4).

6. CB block diagram Bus_CS[i]...Enable[i]

7. LVDS conversion

8. What signals we need from the SPECS slave? We will use 8 I2C buses (1 for CDC and 7 for VFE communication) In the last lhcb-week: Orsay said that there were 8 I2C avalaible more. May be we will use one more for SPD-multiplicity error control. We need also Chip_Select signals from SPECS slave in order to obtain the signal enable[i] to control the direction of LVDS conversion. Orsay said that there was no problem.

9. SPD multiplicity Receive 8x7 bits (number of 1’s in the 64 channels of 8 PS FE). Really there are only 7 or 4 PS cards connected to every SPD multiplicity card. Add the 8 numbers: result of 10 bits. Send the result through one optical link. One small Actel FPGA will do the job.

10. SPD multiplicity Format of the 7 bits data coming from PS FE: LVDS 21:3 (Multiplexed LVDS): (x8) We need only the first 15 bits. Ok? Send to the optical link 10bits+Bx. Data format??? Possibility to send errors (missing Bx...) to ECS via I2C link to the SPECS slave or and Interrupt to the SPECS slave... Will Bx arrive in order? What is the ‘time out’ to assume when a Bx is missing? Next slides we have a first prototype assuming that Bx not arrive in order. Bx indentifier SPD multiplicity‘0’ 21.... 15 14..... 8 7.... 0 MSB LSB

11. SPD multiplicity :LVDS DMUX 3 3 3 33 3 3 3 FPGA I2C to SPECS slave Optical link 15 or 21? Configure number of PS boards connected (7 or 4)

12. Possible implementation... X8 (15 bits: 7data+8Bx)... X8 RAM memory banks of 256 positions X 8bits... data Flag... Bx02 Bx01 Bx00 Bx255 Bx254... If we have 8 bits for Bx identifier there are 256 different possible Bx’s. We have a 8 bit RAM for each channel with 256 positions corresponding the adresses with the Bx identifier. We also have a flag bit to indicate if this memory position is full or empty.

13. Possible implementacion Every time that I receive a Bx from one channel I will write it to the corresponding memory bank (and put the flag bit to 1) and check the flag bit of the same memory position in all the banks. If all the other channel are already occuped I will add the seven channels and I will send the 10 bits result+Bx indentifier through the optical link and I will unflag all the memory bank positions corresponding to this Bx. If I receive a new Bx and the memory position corresponding to it is full I will assume that the last Bx occuping the same memory position is missing (because if the bank is already full there are still empty banks corresponding to the same Bx) and I will report an error through the SPECS slave in the same board..

14. Questions Slave. When? Board to pass data to slave...(mezzanine board) Clock Distribution Chip. When? Or specifications? Is necessary to configure the SPD multiplicity FPGA to work with 8 PS? We have only 7 or 4 PS connected... (less memory, less FPGA pins, less LVDS demultiplexors...) How is the optical link? Can be copied from anywhere? Is the ‘time out’ of 256 Bx explained enough?

15. Next... If SPECS ‘slave’ FPGA is avalaible soon we will start with a first prototype of CB. If ‘slave’ not avalaible we will start with SPD multiplicity...