1. Yanqing Zhang University of Virginia yz4hz@virginia.edu On Clock Network Design for Sub- threshold Circuitry 1

2. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 2

3. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 3

4. Intro: Sub-threshold Operation Voltage scaling leads to quadratic savings in P dyn P dyn = α 0-1 C eff V DD 2 f Scaling is pushed into sub-threshold(sub-V T ) region Transistor devices not “on”… …but still operational Sacrificing performance(speed) for low power/energy Sub-V T characterized by weak drive and long delay And great savings in dynamic power/energy Wide application space Mobile electronics Environmental/body sensor nodes Sub-V T 4

5. Conventionally, H-trees provide: Optimal slew(10%-90% V DD transition time in clock signal) Optimal skew(phase difference between clock signal at difference registers) Slew and skew affect timing constraints CAUSES TIMING VIOLATIONS Intro: Clock Networks for Digital Circuits REG D Q REG D Q logic CLKCLK’ CLK CLK’ Ideal ClockExample H-treePractical Clock Example CLK CLK’ t slew δ 5

6. Intro: Clock Networks for Digital Circuits Timing yield dependant on clock network Setup constraint Hold constraint t c-q, t su, t hold with t slew Clocks designed via clock synthesis Designer has control over t slew,max, C max, δ max module example(…) … endmodule = HDL Coding Logic Synthesis PlacementClock Synthesis[ref]Final Route Well defined. 6

7. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 7

8. Sub-threshold Problems for Clock Network Setbacks of sub-threshold impose difficulty for quality clock network Exponential dependency on V T variation vs Low drive strengths (~10 3 × less) Wire delay no longer a factor Wire load still relevant Direct Impact on Clock Network Both skew and slew Slew also increases short circuit power Skew degradation with process variation[3] Monte Carlo simulation of delay exhibiting non-Gaussian distribution Delay(s) Transistor V gs -I D curve[1] 8

9. Sub-threshold Problems for Clock Network Slew a problem in sub-threshold Short circuit power(not a focus in super-threshold) Low drive strength=less control(10’s ns vs. 1 ps) Scaling won’t work Up to 90% deterministic variation in timing parameters Can re-design directly in sub-threshold, but undermines low power Example of register Scaled Clock Tree [2] 9

10. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 10

11. Slew Aware Clock Tree Design for Sub-threshold Tighter nodal capacitance constraint C MAX will corral slew Slew recovery through buffer is stronger function of C MAX than input slew Therefore, use higher C MAX near clock source, smaller C MAX at registers Relationship between slew, C MAX, and power Output slew vs. load cap and input slew Resulting clock tree shape Resulting optimization [2] 11

12. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 12

13. A Clock Buffer Design for Sub-threshold Problem arises from operating in sub-threshold Solution: circuit in sub-threshold, clock network not Capacitive Boosting: Boosts ‘overdrive’ to higher than V DD No level converter overhead Concept of capacitive boosting[4] 13

14. A Clock Buffer Design for Sub-threshold Shortcomings: Higher static and leakage power/energy for buffer Greater area Not integrated into design flow Complexities with timing and clock gating(1/2 cycle startup) Doesn’t save power at lower frequencies for set V DD Doesn’t necessarily address process variations Advantages: Drastic improvement in slew (2.6x at 0.4V, 1 pF load) Better overall clock network energy due to fewer # of buffers Drastic improvement in skew Improvement in slew[4] Overall improvement in energy consumption for clock network[4] Improvement in skew[4] 14

15. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 15

16. Clock Network Design for Sub-threshold Conventional tree scrutinized Buffers perform poorly, do we really need them? Buffers NOT optimal in face of process variations Case study to compare buffered vs. non-buffered trees vs Buffered vs. non-buffered trees to be compared[3] Energy overhead incurred under same nominal skew constraint for non-buffered trees[3] Skew and slew improvement with non-buffered trees[3] 16

17. Clock Network Design for Sub-threshold Measurements show improvement in skew, skew variation, and slew variation without much overhead 4 orders of magnitude less skew 28% less slew variation 4% power overhead Drawback: design not suitable across all V DD s Drawback: design not suitable across all circuit sizes Drawback: design not suitable across all constraints Skew and slew improvement with non-buffered trees[3] 17

18. Outline Introduction and Motivation Problem Analysis Slew Aware Clock Design for Sub-threshold A Clock Buffer Design for Sub-threshold Clock Topology Discussion for Sub-threshold Summary Questions 18

19. Summary No universal solution Scope and limitations to individual methods Slew Aware Clock Tree Design for Sub-threshold: Good for slew control by design Universal for all clock network topologies Always saves something in power Does not address variations Should be used as an auxiliary method A Clock Buffer Design for Sub-threshold: Fantastic performance with regards to slew and skew Given range of supply voltage that it addresses process variations Ridiculous increase in power/energy for single buffer Thus restricted to certain frequencies and design sizes Clock Network Design for Sub-threshold Method address slew, skew, process variations Power/energy overhead fluctuates with design characteristics What does it all mean? Imminently, no universal solution We should carefully observe the characteristics of our design, and design accordingly Example: Combine papers [3] and [4]? 19

20. References [1] B. H. Calhoun., A. Wang, N. Verma, A. P. Chandrakasan, "Sub-threshold Design: The Challenges of Minimizing Circuit Energy," International Symposium on Low Power Electronics and Design (ISLPED), pp. 366- 368, October 2006. [2] J. R. Tolbert, X. Zhao, S. K. Lim, S. Mukhopadhyay, “ Slew-Aware Clock Tree Design for Reliable Subthreshold Circuits”, ISLPED, August 2009. [3] Jonggab Kil, et al, “A High-Speed Variation-Tolerant Interconnect Technique for Sub-threshold Circuits Using Capacitive Boosting,” ISLPED, 2006, pp. 67-72. [4] Mingoo Seok, D. Blaauw, D. Sylvester, "Clock Network Design for Ultra-Low Power Applications,"International Symposium on Low Power Electronics and Design, Aug, 2010. 20

21. Questions? 21