1. Status of FTK Paola Giannetti INFN Pisa for the FTK Group ATLAS Italia November 17, 2009

2. Status & Evolution 2 10 34 WH(120) →lv bjet-bjet, Hqq →  jet-  jet qq, isolated leptons : DONE o New architecture o good performances on b-jets and  -jets o new application: muon & electron isolation 3 x10 34 : to be DONE for end 2009 o performance studies: ongoing o More powerful architecture: in evolution After approval split into 2 activities o vertical slice @CERN (start 2011) → protoFTK studies → insertion new prototypes → 10 34 o build the system for 3 x10 34 (2015?)

3. σ FTK = σ offline ⊕ 30μm WH 10**34 pile-up WH 11 L 10**34 cm IP resolution RMS=87  RMS= 72  IPAT FTK IPAT FTK FTK WH 3x10 34 FTK single  Offline single  3x10 34 as good as single  & 10 34 ATHENA full Simulation + FTKsim IP resolution RMS=69  IPAT FTK nPix+nSCT hits >=10 |d|<2.2 mm pT > 1 GeV chi2/dof < 4 3x10 34

4. 4 RORO RIRI RSRS leading P T track Jet axis |  | < 0.8 for jet 10 33 Lumi Fakes as a function of jet  Fakes as a function of jet Pt iPat Tracks FTK Sim Tracks  -jet efficiency rejection Single Prong (1,0) Efficiency vs.  Efficiency vs. p T

5. τ-tagging Performance 5 1-prong efficiency similar to using offline tracks for the same algorithm, with very low fake rate (barrel-only) Good efficiency at 10 33 & 10 34 3-prong efficiencies are also similar FTK tracks iPat tracks qqH(120)  qq  QCD jetsqqH(120)  qq  1-prong (1,0) 3-prong (3,0) 10 33 10 34 10 33

6. track-based isolation with z0 of all tracks in the cone within 10mm of the muon track z0

7. Near-term Plans 7 Detailed analysis of 3x10 34 samples o b, τ, μ, e performance with baseline algorithms o improved b, τ tagging performance with algorithms that make use of the freed-up L2 time o FTK timing (data flow) o Default L2 timing Complete TDR (end of the year) Be approved (beginning 2010) ITALIAN Institutions (up to now): PISA – FRASCATI – BOLOGNA (vertical slice)- PAVIA (vertical slice)

8. FTK WH 3x10 34 FTK single  ATHENA full Simulation + FTKsim FTK WH 3x10 34 FTK single  Pt resolution

9. 9 1/2  AM Divide into  sectors 6 buses 40MHz/bus (to be increased) ATLAS Pixels + SCT Feeding FTK @ 100kHz event rate Pixel barrelSCT barrelPixel disks 11 Logical Layers: full  coverage 8  regions each with 6 sub-regions (  towers)  ~25 o,  ~1.7 bandwidth for up to 3*10E34 cm -2 s -1 Allow a small overlap for full efficiency

10. 10 Track data ROB Track data ROB Raw data ROBs ~Offline quality Track parameters … HITS CHANGES FOR 10 34 Pixels & SCT Data Formatter (DF) 50~100 KHz event rate RODs cluster finding split by layer cluster finding split by layer overlap regions overlap regions Remove duplicate trks S-links Data Organizer AM brd Track Fitter Data Organizer AM brd Track Fitter 6x  towers SUPER BINS DATA ORGANIZER ROADS ROADS + HITS EVENT # N PIPELINED AM+RW HITS DO-board EVENT # 1 2 nd step: track fitting TRACK FITTER + HW cleaning AM-board NEW

11. 11 DO-TF DO AMBoard+RW TSP X 6 = 12 AMBoard + 6 DO + 6 TF gruped like this= 3x6=18 slots TF DO FOR 11 LAYERS BUT ONLY ROADS IN 2 AMBOARDS New Crate Layout for 10 34 AUX board Looks similar if look in front of it But on the back more cards! More dense boards! OLD NEW

12. BUT 3x10 34 is horribly worse! 12 We have succeeded in running digitization at 3x10 34 by turning off cavern background and reducing the range of bunch crossing for pile-up (still with the full range for tracking) The number of silicon hits is large! We are currently running these through FTK simulation Huge number of roads (fired patterns) found → increase resolution

13. Possible Architectures- @ 3x10 34 13 1)Two pattern banks offset by ½ SS Require road to be found in both. Reduced effective SS width decreases # of combinations w/ small (x2) increase in pattern bank size 2)Tree Search Processor (TSP) Smaller SS binary search after AM. Reduces SS size  fewer combinations 3)Split Architecture First find SCT tracks, then fit with pixels (ala CDF SVT). Avoid 11L combinatorics by only taking good fits 1234 5678 1 2 3 4 Number of fits is not any more a problem SCT layers alone are blind because of too large number of firing roads even at very high resolution Heavily used

14. FPGA LAMB Standard cell chip 40 MHz clock AUX card Connectors for LVDS Cables FIFOS Replaced By FPGA AMBoard with TSP for each LAMB MINI DO + TSP New Organization inside the AMBoards: TSPs in the AUX board and below each LAMB to fight fakes gradually: 4 kroads from Lamb → 400x4 from AMboard→ ~300 from AUX DRIVERS RECEIVERS LVDS

15. The AM chip R&D to design the new full custom cell for patterns (M.Beretta Frascati, L.Sartori & E. Bossini Pisa). Copy the CAM structure. First small 90 nm prototype in 2010. We hope to gain between a factor 4 and 8 as pattern # (reduced size of the pattern) Possible collaboration with Fermilab to try the 3D technology. Not yet started. Trying to evaluate possible advantages. First attempt: 4 130 nm layers each one made exactly equal to the already existing CDF AM chip (1 cm 2 large area): measure the yeld, the consumption…..

16. Backup October 29, 200916

17. Algorithm: NIM A287 (1990) 436-438 http://www.pi.infn.it/~paola/Tree_search_algorithm.pdf Tree Search Processor: NIM A 287, 431 (1990), http://www.pi.infn.it/~orso/ftk/NIMA287_431.pdf IEEE Toronto, Canada, November 8-14 1998 http://www.pi.infn.it/~paola/TSP_v14.pdf 1 2 3 4 THIN ROAD FAT ROAD Found by AM (default SS for example or even larger) 1234 5678 Depth 0 Depth 1 Depth 2 PATTER N BLOCK PARENT PATTERN Advantages:  pattern bank saved in dense RAMs  high degree of parallelism

18. μ Trigger at High Luminosity 18 The default muon trigger uses calorimeter and tracking information, but the calorimeter is sensitive to pile-up o This is drastically improved with the use of tracking information: track-based isolation requiring that the z0 of all tracks in the cone is within 10mm of the muon (inner detector) track z0

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23. October 29, 200923 Pattern Recognition Massively parallel processing o A large bank of pre-computed hit patterns is used for very fast tracking (memory  speed) Linearized track fit using full-resolution silicon hits after pattern recognition Current chip used in CDF SVT: 0.18 μm standard cells, with 5000 patterns/chip. IEEE Trans.Nucl.Vol. pp 2428-2433 SuperStrip (SS)

24. Track Fitting October 29, 200924 Linear approximation 14 coordinates  5 helix parameters & 9 constraints The “fit” is just multiplies & accumulate, ideal for a DSP FPGAs with hundreds of DSP slices reach 1 nsec/track fit Resolutions approach that of offline quality New: Store partial results for faster 10/11 calculation P i : 5 track parameters & 9 constraints x j : the hit coordinate in layer j a ij, b i : the stored constants for each sector, pre-computed in from a large sample of training tracks (simulation or data)

25. 25 A hardware architecture able to digest WH  lnubb + 10 34 pileup @ 75kHz event rate SUPER Bins DO + TF HITs ROADS 12 L SUPER Bins DO + TF HITs ROADS 12 L ….….……..  Tower 0  Tower 5 TRACKS TRACKS MERGING + HW Tracks to Level 2 1000 hit/ev/layer corrected for overlaps between region → 1000/3=330/ev. Dividing in 6  towers (with 100% contingency for tower overlap) → 330 * 75 kHz = 25 MHz OK even for current AMchip! ~6500 /ev → 3600 for RW reduction → 600/ev if divided in 6 engines → 600 * 75 kHz = 45 MHz →1 Road each 22 ns 400 k /ev. → 66 k /ev. in 6 engines → 66 k * 75 kHz → 5 G /s → 5 fit/ns 1 FTK core crate : 6  towers