1. University of Tehran 1 Microprocessor System Design Omid Fatemi

2. University of Tehran 2 Outline 80x86 history Minimal / Maximal mode Address latch enable Bi-directional data bus

3. University of Tehran 3 Computer modules CPU Memory (RAM, ROM) Peripherals (IO) Data Bus Control Bus Address Bus Keyboard Monitor Printer Mouse Microphone Disk

4. University of Tehran 4 Memory Von Neumann Architecture Data Microprocessor Registers Actual Processor Program Address Lines Data Lines Control Lines

5. University of Tehran 5 The 8086 Family:The Late 1970’s Could address up to 1 mb of memory at a time when other CPU’s could only address 64 kb. The 16 bit external bus too powerful. The 8088 replaced the 8086 and had only an 8 bit external bus

6. University of Tehran 6

7. University of Tehran 7 The 80286 Family:1983 Wanted to make the 286 backward compatible with the 8088’s. So had 2 modes: –Real mode-less powerful –Protected mode-very powerful »Could access up to 16 mb of memory »Needed a special operating system But most users only had DOS

8. University of Tehran 8 The 386DX: 1985 First true 32 bit chip, all buses 32 bits wide Capable of running in real mode, 286 protected mode and its own 386 protected mode In 386 protected mode it had a new function: –Virtual memory- could use hard drive to pretend that computer had up to 4 GB of data!

9. University of Tehran 9 The 386SX:1988 How different from the 386DX? –External data bus reduced to 16 bits –Address bus reduced to 24 bits, which limited memory use to 16 mb –First popular laptops were based on the 386SX but was called the 386 SL and ran on 3.3 volts

10. University of Tehran 10 The 486DX:1989 How different from the 386 family? –A built in math coprocessor »Performs high math functions –A built in 8K cache on same chip »This was an SRAM cache that stores code read in the past. When the CPU asks for the code again, it doesn’t have to go to DRAM to get it.

11. University of Tehran 11 The Pentiums:1993 Had 64 bit external data bus that split internally as 2 dual pipelined 32 bit buses Most early Pentiums ran at 3.3 volts.

12. University of Tehran 12 Pentiums continued Most later Pentiums use SPGA, (Standard Pin Grid Array). This allows staggering the pins and allows for higher pin density

13. University of Tehran 13 Latest CPUs Intel64 –64-bit linear address space –Pentium Extreme, Xeon, Celeron D, Pendium D, Core 2, and Core i7

14. University of Tehran 14 8088 Microprocessor Minimum Mode

15. University of Tehran 15 Pin Configuration

16. University of Tehran 16 8086 Signals

17. University of Tehran 17 Providing Clock, Reset, and Ready Signal

18. University of Tehran 18 Minimum Mode

19. University of Tehran 19 Minimum Mode

20. University of Tehran 20 Minimum Mode

21. University of Tehran 21 Minimum Mode MEMORY D7 - D0 A7 - A0 A15 - A8 A19 - A16 RD WR 8088 AD7 - AD0 A15 - A8 A19/S6 - A16/S3 DEN DT / R IO / M RD WR ALE

22. University of Tehran 22 Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read ALE T1 CLOCK T2T3T4 AD7 - AD0 A15 - A8 A19/S6 - A16/S3 DT/R __ IO/M __ ____ RD DEN ______ A15 - A8 A7 - A0D7 - D0 (from memory) A19 - A16S6 - S3 if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW

23. University of Tehran 23 Will the circuit be able to perform memory read? ;assume that initially the values ;of the registers are: ;BX = 1234, DS = 9000 MOV AL, [BX]

24. University of Tehran 24 Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read ALE T1 CLOCK T2T3T4 AD7 - AD0 A15 - A8 A19/S6 - A16/S3 DT/R __ IO/M __ ____ RD DEN ______ A15 - A8 A7 - A0D7 - D0 (from memory) A19 - A16S6 - S3 if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW

25. University of Tehran 25 Minimum Mode MEMORY D7 - D0 A7 - A0 A15 - A8 A19 - A16 RD WR 8088 AD7 - AD0 A15 - A8 A19/S6 - A16/S3 DEN DT / R IO / M RD WR ALE

26. University of Tehran 26 Minimum Mode MEMORY D7 - D0Q7 - Q0 OE LE 74LS373 D7 - D0Q7 - Q0 OE LE 74LS373 D7 - D4Q7 - Q4 OE LE D3 - D0Q3 - Q0 74LS373 GND D7 - D0 A7 - A0 A15 - A8 A19 - A16 RD WR 8088 AD7 - AD0 A15 - A8 A19/S6 - A16/S3 DEN DT / R IO / M RD WR ALE

27. University of Tehran 27 Octal Transparent Latch with 3-State Output

28. University of Tehran 28 Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read ALE T1 CLOCK T2T3T4 AD7 - AD0 A15 - A8 A19/S6 - A16/S3 DT/R __ IO/M __ ____ RD DEN ______ A19 - A0 from 74LS373 to memory A7 - A0D7 - D0 (from memory) S6 - S3A19 - A16 A19 - A0 from 74LS373 if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW A15 - A8

29. University of Tehran 29 Will the circuit be able to perform memory read? ;assume that initially the values ;of the registers are: ;BX = 1234, DS = 9000 MOV AL, [BX]

30. University of Tehran 30 Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read (with 74373)

31. University of Tehran 31 Minimum Mode What about Data read and write

32. University of Tehran 32 Minimum Mode MEMORY D7 - D0Q7 - Q0 OE LE 74LS373 D7 - D0Q7 - Q0 OE LE 74LS3738088 AD7 - AD0 A15 - A8 A19/S6 - A16/ S3 DEN DT / R IO / M RD WR ALE D7 - D4Q7 - Q4 OE LE 74LS373 D3 - D0Q3 - Q0 GND D7 - D0 A7 - A0B7 - B0 E DIR 74LS245 A7 - A0 A15 - A8 A19 - A16 RD WR

33. University of Tehran 33 Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read (with 74245)

34. University of Tehran 34 CLK M/IO ALE ADDR/ DATA ADDR/ STATUS DT/R DEN T1T2T3T4 A15-A0 A19-A16 DATA OUT (D15-D0) WR Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Write (with 74245)

35. University of Tehran 35 Minimum Mode

36. University of Tehran 36 Minimum Mode

37. University of Tehran 37 Minimum Mode

38. University of Tehran 38 Minimum Mode