1. T ECHNIQUES F OR L OW -P OWER -ASIC D ESIGN JTAG Ismael Firas 1

2. I NTRODUCTION Low Power design is all about reducing one or several parts of the power equation. Dynamic power. Leakage/Static power. 2

3. In the past: Over all power density has essentially stayed the same for every process reduction. ITRS Prediction in 2005: at 65-nm node dynamic power density and leakage power density would increase by 1.43 and 2.5, respectively. at 45-nm node we will get 2 and 6.5 respectively. In realty : at 65-nm designs, processes lose as much as half their power to leakage. at 45-nm node, leakage power consumes 60% of an ICs total power. 3

4. 4 ITRS: International Technology Roadmap for Semiconductors

5. I NCREASE D ESIGN P ERFORMANCE AND SIDE EFFECTS. 5 Using new Materials: Low-k dielectrics. Copper. Using new techniques: Smaller geometries. Lower supply voltage, power dissipation is proportional to (V DD )^2. Lower transistor threshold voltage, V TH. Side effects: Leakage/Static power. Sub-threshold leakage. Gate leakage.

6. D RAMATIC SIDE EFFECT ON LEAKAGE 6

7. 7 F ACING L OW -P OWER SIDE EFFECTS

8. M OST POPULAR T ECHNIQUES FOR L OW -P OWER -D ESIGN Clock gating. Power-aware memories. Multi-threshold design. Multi-voltage design. Power gating. 8

9. C LOCK GATING : Simple concept : If you don’t need a clock running, shut it down. Simple implementation: Now synthesis tools can automatically do it. Two popular methods: Local Using clock-gating cell: replacing feedback multiplexer. Global Turn of the clock to the whole block. 9

10. L OCAL AND G LOBAL CLOCK - GATING 10

11. P OWER - AWARE MEMORIES Effective for lowering both, dynamic power and leakage power. Techniques: Simple concept: shut down segments of memory array when they are not in use. Multi-mode power. Dual-function memories. 11

12. M ULTI - THRESHOLD D ESIGN : Addresses leakage power mainly. Basic requirements are different threshold voltage libraries of the same cell’s functionality, and a power-aware implementation tool. Threshold voltage libraries: Standard/nominal library. High-speed library. Low-power library. Nonlinear relationship: High threshold voltage slower but less leakage. Low threshold voltage faster but leak. 12

13. M ULTI - VOLTAGE D ESIGN : Helps designers control dynamic power. Critical paths/blocks get access to max voltage. Reduce the voltage to Less power-hungry blocks. Using level-shifters between blocks with different voltages. Simple concept but complex implementation. EDA tools helps with implementation but RTL problem appears. 13

14. P OWER GATING / MTCMOS Complex technique but very promising. Shutdown blocks in design when are not in use. Power controller design starts at RTL. Techniques: Fine-grained: switch transistor between ground and each gate. Coarse-grained: using power-switch network. Medium-grained: a compromise between two techniques. 14

15. P OWER - GATING TRANSISTORS 15

16. R EDUCING LEAKAGE USING DIFFERENT TECHNIQUES 16

17. EDA – E LECTRONIC D ESIGN A UTOMATION Category of tools for designing and producing electronic systems. help designers implement low-power-design techniques. Cadence’s CPF-Common power format. A few small EDA companies. Accellera’s UPF-Unified power format. Synopsys, Mentor, Magma. 17

18. CONCLUSION The EDA industry still has much work to do before it can solve the power problem. Designers must become familiar with a mix of low-power-design techniques. 18