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Full-Custom Design ….TYWu

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Presentation on theme: "Full-Custom Design ….TYWu"— Presentation transcript:

1 Full-Custom Design ….TYWu

2 Outline Introduction Transistor Process Steps Layout Schematic R/C
Design Rules Tools

3 Layout Terminology: Contacts, Vias, etc. Vias Contacts metal 3 metal 2
poly poly p-tub n+ n+

4 Layout Different Technologies May Have Different Layer Information
Total Number of Layers Layer ID Examples TSMC 0.18um: 6 Metal Layers TSMC 0.25um: 5 Metal Layers TSMC 0.35um: 4 Metal Layers

5 Layout Example for Layer Information GDS Layer Layer Name Description
25 CONTACT Generic Contact (to Poly or Active) 42 N_WELL N-well implant 43 ACTIVE Active area 44 P_PLUS_SELECT P+ diffusion 46 POLY Polysilicon 47 POLY_CONTACT Contact to Poly : 62 METAL3 Third layer metal

6 Layout Hercules runset for Layer Information :
ASSIGN { NWELL (2)} /* N-Well */ ASSIGN { OD (11,12,3)} /* thin oxide */ ASSIGN { OD (4)} /* Thick Oxide */ ASSIGN { PIMP (7)} /* P+ S/D Implantation */ ASSIGN { NIMP (8)} /* N+ S/D Implantation */ ASSIGN { LPP (48)} /* Lightly P+ Poly Implant */ ASSIGN { POLY1 (13)} /* Poly Si */ ASSIGN { POLY2 (14)} /* Poly2 for caps and res */ ASSIGN { CONT (15)} /* Contact */ ASSIGN { M (16)} /* Metal-1 */ ASSIGN { VIA1 (17)} /* Via1 Hole */ ASSIGN { M (18)} /* Metal-2 */ ASSIGN { VIA (27)} /* Via2 Hole */ ASSIGN { M (28)} /* Metal-3 */ ASSIGN { VIA3 (29)} /* Via3 Hole */

7 Layout Using Different Patterns or Colors to Represent Different Layers

8 Layout Using Different Patterns/Colors to Represent Different Layers (Virtuoso)

9 Layout Using Different Patterns/Colors to Represent Different Layers
Common layout layers

10 Layout Using Different Patterns/Colors to Represent Different Layers (L-Edit)

11 Layout Using Different Patterns/Colors to Represent Different Layers

12 Layout An Illustration of Drawing an Inverter P substrate wafer n well

13 Layout Inverter

14 Layout Layout of an inverter

15 Layout Layout and Cross-section of an inverter (β ratio=?)

16 Layout L/W for NMOS Transistor L w L

17 Layout

18 Layout Diode I I N+ O O O I

19 Layout Resistor

20 Layout Resistor

21 Layout Capacitor

22 Layout Parasitic SCR

23 Layout Parasitic SCR circuit I-V behavior I

24 Layout CMOS ICs have parasitic silicon-controlled rectifiers (矽控整流器: SCRs). When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures.

25 Layout Solution to latch-up
Use tub ties to connect tub to power rail. Use enough to create low-voltage connection n+ n-tub oxide VDD

26 Layout Tub tie layout metal (VSS) p-tub p+

27 Layout Solution to latch-up Minimize Rw and Rs Substrate Contact

28 Layout Solution to latch-up

29 Layout Power Resistance of power supply line must be very small
If too large, then the voltage supplied to gates will drop (why?), which may cause malfunction of gates So, power supply lines must be wide metal Rtrans >> Rmetal Not so easy since wires are long and transistors are large

30 Layout IR Drop Example (100K gate chip) Considerable IR drop!
Each gate drives 1mm wire (200fF) in 500ps I = C dV/dt = 200fF x 2.5V / 500ps = 1mA If all switch at once, 100A! Even if only 10% switch at once, still 10A peak current! Considerable IR drop! Need many supply pins, wide power supply wires

31 Layout Power Distribution

32 Layout Cell-based chip will appear like

33 Layout Standard Cells General purpose logic Can be synthesized
Same height, varying width

34 Layout Standard Cells

35 Layout Standard Cell Layout Methodology No Routing channels VDD VDD M2
: Mirrored Cell No Routing channels VDD VDD M2 M3 Standard Cell GND Mirrored Cell : GND

36 Layout Standard Multi-Finger Transistor (Parallel)

37 Layout Standard Cell W=10 W=20 Multi-Finger Transistor One finger
Two fingers (folded) W=10 W=20 Less diffusion capacitance

38 Layout Standard Cell Multi-Finger Transistor
Gate resistance becomes small Less diffusion capacitance

39 Layout Standard Cell Cell height 12 metal tracks
N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” V DD Out In GND Cell boundary

40 Layout Standard Cell A Out V DD GND B 2-input NAND gate

41 Layout Exercise B V DD A Out2

42 Outline Introduction Transistor Process Steps Layout Schematic R/C
Design Rules Tools

43 Schematic Composer & Virtuoso Schematic Symbol Layout Layout Library

44 Schematic Composer (Command: icfb) Create a New Library

45 Schematic Create Schematic 此 cell 是以設計 NAND gate 為例子 Schematic Design

46 Schematic Construct Your Design

47 Schematic CDL out: schematic view  Spice netlist

48 Schematic Spice Netlist For LVS : *.PININFO y:O a:I
.subckt nand02d1_schematic vout a b MN1 vout b net10 GND n w=500u l=350u MN0 net10 a GND GND n w=500u l=350u MP1 vout a VDD VDD p w=1u l=350u .ends nand02d1_schematic

49 Schematic Design Flow in Goya Composer Laker Calibre Star-RCXT H-Spice
Circuit Designers Layout Engineers Layout Engineers Layout Engineers Circuit Designers Composer Laker Calibre Star-RCXT H-Spice A Out V DD GND B LVS DRC

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