1. FP7 Uniboard project Digital Receiver G. Comoretto, A. Russo, G. Tuccari, A Baudry, P. Camino, B. Quertier Dwingeloo, February 27, 2009

2. Framework Wideband radioastronomy receivers  Instantaneous BW 4-12 GHz  Digitizers: current 1-2 GHz, near future 4-8 GHz Digital hardware: limited by clock, 100-300 MHz bandwidth → Need for frequency multiplexing Multibeam receivers  Tens → hundreds of pixels 7 feed FP5 Faraday receiver

3. Existing systems DBBC  4x 1GHz BW, up to 16 Virtex5 cores  EVN standard: 4 cores = VLBI terminal  DBBC3: wider band ADC3 & V.6 core MPI-Agilent FFT Spectrometer  1 GHz BW, Virtex4 core  Up to 8 boards on a PCI bus Casper  Up to 1.5 GHz BW, 1x (IBOB) or 5 x Virtex2 (BEE2)  ROACH: Virtex-5 based Avoid duplications! Keep an open path to future apps & HW ROACH DBBC

4. Specifications Input:  Bandwidth: 4 GHz (8 GS/s)  Quantization: 6 bit minimum (8 bit possible)  Future development, 2-3 yrs: 8 GHz 4-6 bit  Format: data on several 10G links, one sample per link, time multiplexed Output:  Bandwidth: up to 64 MHz/channel (128 MS/s), up to 64 channels  Quantization: 1, 2, 4, 8 bit  Format: Standard MK5C format, UDP packets, on 10G links Each channel position and BW independently selectable (with limitations) Everything fits in a single board

5. General structure Two stage filter 1 st stage:  Polyphase FFT  real input  32x250MHz complex output, divided into 8 groups  125 MHz channel spacing 2 nd stage:  Tunable filter: LO/mixer, low-pass FIR, complex-to-real  4 sets of 16 FIRs  Each set selects input among a 1st stage channel group

6. High SFDR using polyphase filter 8 GHz BW likely affected by RFI RFI mitigation by excision of affected spectral region Good chan.-to-chan. rejection to avoid contamination 18 bit multipliers: limit to ~85 dB SFDR Filter design: 85 dB stopband 96% useful BW, 0.04 dB ripple >90 dB with 94% BW channel 3 channel 2 channel 1 Channels overlapped to avoid holes Out BW

7. FFT general structure DIT FFT algorithm Optimized for real input: minimum number of complex mults Complex conjugate outputs not computed Divided in 2 sections: 4 x radix-16 (local) & 4x radix-4 (global) Butterfly Complex multiplier

8. How to fit in the Uniboard Uniboard structure: 4 input + 4 output FPGAs Each FPGA has 2x10G in/out No vertical interconnect 4x4 fixed interconnect between input and output FPGAs 2.5 Gbps per link  250 MS/s @ 8 bit

9. 2 stage DIT FFT Decimation in time FFT algorithm:  separate data flow for parallel decimated samples Limitation in interconnections: only selected channels processed

10. Channels and groups 32 overlapping channels ½ channel spacing Channels are grouped in groups of 4 Groups 0, 1, 2, 3 Groups 4, 5, 6, 7 Up to 4 groups available at each time: segmented coverage of whole 4 GHz (with edge holes, ~4% lost) or continuous coverage of narrower band

11. Implementation - 1 st FPGA 610 hard multipliers required Total power needed for proper re-quantization Dynamic selection of output channel groups

12. Implementation - 2 nd FPGA Input butterfly require little resources => all resources available for application 16 Tunable DBBC implementable in Virtex5 chip – 32 in Stratix4 Alternative use:  a 4096 pts FFT spectrometer require ~70 multipliers: up to 8 FFT per chip

13. 8 bit between stages enough? Limited BW between input and output FPGAs: max 256MS @ 8 bit per link Requantization with 8 bit may degrade SFDR Tests with Gaussian noise + spectral line in 1 channel > 80 dB SFDR observed

14. 6 bit may be sufficient Tests with 6 bit quantization show > 65dB SFDR Difficult to assess, need very long test vectors 3.7 GB link & 6bit: all 32 channels can be analyzed Full coverage of 4 GHz BW Possible coverage of future 8 GHz BW

15. 2 nd stage FIR Derived from ALMA Tunable Filterbank Variable Decimation FIR Filter: D=2-256  Taps: 32*D, tap recirculation, symmetric  32 (2x16, real-imaginary) multipliers Output conversion to real by ½ band shift Specifications TBD.  Example from ALMA design  18 bit required for high rejection  Tradeoff between complexity and performances Example: filter performance for 9 bit, 94% BW, 16 multipliers ½ to 1/256 BW

16. Conclusions 4 GHz BW, 64 tunable channels system feasible in a single Uniboard 4x1GHz bypassing 2 nd butterfly (but easier w. DBBC!) 8 GHz BW feasible (Phase 2 of the project) >80 dB spurious free dynamic range (may improve) Applications  Front-end for other systems  VLBI channelization system  FFT very wide band spectrometer (e.g. 4GHz 64k pts)