1. TIMERS

2. TIMER 0 MODULE • 8-bit timer/counter
The Timer0 module has the following features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt on overflow from FFh to 00h
• Edge select for external clock

3. OPTION_REG Register (Address 81h,181h)
PSA
PS2
PS1
PS0
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2:0 PS2:PS0:
TMR0 Prescaler/WDT
Postscaler Rate Select bits

4. bit 5 T0CS: TMR0 Clock Source Select bit
T0ES
PSA
PS2
PS1
PS0
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI
pin
0 = Increment on low-to-high transition on T0CKI

5. TOSC=‘0’ Timer mode
Timer0 module will increment every instruction cycle (without prescaler).
TOSC=‘1’ Counter mode
Timer0 will increment either on every rising or falling edge of the T0CKI pin.
T0SE=‘0’ Rising edge
T0SE=‘1’ Falling edge

6. Internal Clock/No Prescale
After the TMR0 register has been written with the new value, TMR0 will not be incremented until the third instruction cycle later.
Internal Clock/No Prescale
Internal Clock/Prescale

7. T0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h T0IF=‘1’
The interrupt can be masked by clearing bit T0IE
The TMR0 interrupt cannot awaken the
processor From SLEEP since the timer is
shut-off during SLEEP.

8. T0IF=‘1’ Option Register PSA PS2 PS1 PS0 X X 0 X 0 0 0 0 RBPU INTEDG
T0CS
T0ES
PSA
PS2
PS1
PS0
X X X
T0IF=‘1’

9. RBPU
INTEDG
T0CS
T0ES
PSA
PS2
PS1
PS0
X X
T0IF=‘1’

10. T0IF=‘1’ Option Register PSA PS2 PS1 PS0 X X 1 0 1 0 0 0 RBPU INTEDG
T0CS
T0ES
PSA
PS2
PS1
PS0
X X
T0IF=‘1’

11. Changing Prescaler (WDT Timer0)
CLRWDT ; Clear WDT and prescaler
BSF STATUS, RP ; Bank1
MOVLW b'xxxx0xxx' ; Select TMR0, new prescale
MOVWF OPTION_REG ; value and clock source
BCF STATUS, RP ; Bank0

12. Changing Prescaler (Timer0 WDT)
BSF STATUS, RP ;Bank1
MOVLW b'xx0x0xxx' ;Select clock source and prescale value
MOVWF OPTION_REG ;other than 1:1
BCF STATUS, RP ;Bank0
CLRF TMR ;Clear TMR0 and prescaler
BSF STATUS, RP ;Bank1
MOVLW b'xxxx1xxx‘ ;Select WDT, do not change prescale value
MOVWF OPTION_REG ;
CLRWDT ;Clears WDT and prescaler
MOVLW b'xxxx1xxx' ;Select new prescale value and WDT
BCF STATUS, RP ;Bank0
RBPU
INTEDG
T0CS
T0ES
PSA
PS2
PS1
PS0

13. Timer0 Initialization (Internal Clock Source)
CLRF TMR ; Clear Timer0 register
CLRF INTCON ; Disable interrupts and clear T0IF
BSF STATUS, RP0 ; Bank1
MOVLW 0xC3 ; PortB pull-ups are disabled,
MOVWF OPTION_REG ; Interrupt on rising edge of RB0
; Timer0 increment from internal clock
; with a prescaler of 1:16.
BCF STATUS, RP0 ; Bank0 ;
; The TMR0 interrupt is disabled, do polling on the overflow bit
T0_OVFL_WAIT
BTFSS INTCON, T0IF
GOTO T0_OVFL_WAIT ; Timer has overflowed
RBPU
INTEDG
T0CS
T0ES
PSA
PS2
PS1
PS0

14. Timer 1 Module

15. 16 bit timer/counter module
Interrupt bit flag TMR1IF(PIR1<0>)
Prescaler 1,2,4,8
3 Modes operations:
Timer
Synchronous Counter
Asynchronous Counter
0000h-FFFFh
0-65,535
TMR1H
TMR1L

16. T1CON: Timer1 Control Register
TMR1CS
TMR1ON
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

17. bit 3 T1OSCEN: Timer1 Oscillator Enable bit
T1SYNC
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Oscillator is enabled
0 = Oscillator is shut off. The oscillator inverter and feedback
resistor are turned off to eliminate power drain
bit 2 T1SYNC: Timer1 External Clock Input
Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

18. bit 5:4 T1CKPS1:T1CKPS0: Timer1 Input Clock
_____
T1CKPS1
T1CKPS0
bit 5: T1CKPS1:T1CKPS0: Timer1 Input Clock
Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value

19. Timer Mode
TMR1CS=‘0’
Input clock to the timer is FOSC/4
T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync.

20. Synchronized Counter Mode
TMR1CS=‘1’ & T1SYNC=‘0’
Timer increments on every rising edge of clock input on the T1OSI pin when the oscillator enable bit (T1OSCEN) is set, or the T1OSO/T1CKI pin when the T1OSCEN bit is cleared.
In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off.

21. Asynchronized Counter Mode
TMR1CS=‘1’ & T1SYNC=‘1’
Timer continues to increment asynchronously to the internal phase clocks
Timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake-up the processor
For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register

22. Timer1 Block Diagram
T1CON X

23. Timer1 Block Diagram
T1CON

24. Timer 2 Module

25. Timer 2 Module 8 bit timer TMR2 0h-ffh (0-255) T2CON
8 bit register PR2
Interrupt bit flag TMR2IF(PIR1<1>)
Prescaler 1:1, 1:4, 1:16
Postscaler 1:1 – 1:16
One mode operation (Fosc/4)

26. T2CON bit 1:0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

27. TMR2ON
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off

28. bit 6:3 TOUTPS3:TOUTPS0: Timer2 Output 0000 = 1:1 Postscale _
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
bit 6:3 TOUTPS3:TOUTPS0: Timer2 Output
Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale •
1111 = 1:16 Postscale

29. The prescaler and postscaler counters are cleared when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (POR, MCLR Reset, WDT Reset or BOR)
TMR2 is not cleared when T2CON is written.
During sleep, TMR2 will not increment. The prescaler will retain the last prescale count, ready for operation to resume after the device wakes from sleep.

30. TIMER2 BLOCK DIAGRAM

31. MOVLW 0x72 ; Postscaler = 1:15, Prescaler = 1:16
CLRF T2CON ; Stop Timer2, Prescaler = 1:1,
; Postscaler = 1:1
CLRF TMR ; Clear Timer2 register
CLRF INTCON ; Disable interrupts
BSF STATUS, RP0 ; Bank1
CLRF PIE1 ; Disable peripheral interrupts
BCF STATUS, RP0 ; Bank0
CLRF PIR1 ; Clear peripheral interrupts Flags
;============================================
MOVLW 0x ; Postscaler = 1:15, Prescaler = 1:16
MOVWF T2CON ; Timer2 is off
BSF T2CON, TMR2ON ; Timer2 starts to increment ;
; The Timer2 interrupt is disabled, do polling on the overflow bit
T2_OVFL_WAIT
BTFSS PIR1, TMR2IF ; Has TMR2 interrupt occurred?
GOTO T2_OVFL_WAIT ;NO, continue loop
; Timer has overflowed
BCF PIR1, TMR2IF ; YES, clear flag and continue.