1. 微算機原理與應用實習 Holtek 48R70A

2. The Architectures of Microprocessor – 哈佛架構 (Harvard architecture) – 汎紐曼架構 (von Neumann architecture) The Instruction Set of Microprocessor –RISC: Reduced Instruction Set Computer –CISC: Complex Instruction Set Computer I/O Addressing –I/O mapped I/O –Memory mapped I/O Performance Measurement –MIPS: Million of Instruction Per Second Background

3. General Computer Architecture 5-unit –ALU, Memory, Input, Output, Control

4. Microcontroller or Single Chip

5. Introduction to HT48R70A

6. HT48R70A Features Operating voltage: –fSYS=4MHz: 3.3V~5.5V –fSYS=8MHz: 4.5V~5.5V 56 bidirectional I/O lines (max.) 1 interrupt input 2*16-bit programmable timer/event counter and overflow interrupts On-chip RC oscillator, external crystal and RC oscillator 32768Hz crystal oscillator for timing purposes only Watchdog Timer 8192*16 program memory ROM 224*8 data memory RAM HALT function and wake-up feature reduce power consumption 16-level subroutine nesting Up to 0.5s instruction cycle with 8MHz system clock at VDD=5V Bit manipulation instruction 16-bit table read instruction 63 powerful instructions All instructions in one or two machine cycles 48-pin SSOP, 64-pin QFP package

7. 48R Serials I/O Type Block Diagram

8. Interrupt Timer1 Timer0 Watch dog I/O Port 48R70A Hardware Architecture

9. Pin Assignment

10. I/O Pins Port A, Port B, Port C, Port D, Port E, Port F, Port G Each Port Can be set to Schmitt Input or CMOS Output by Software Port A can use ROM option to set –Wake-up –Pull-high Port B, C, D, E, F, G can be set to Pull-high by ROM option INT#In 外部中斷訊號，為史密特觸發、無提昇電阻之輸入腳。 為負邊緣觸發 ( 即由 high 到 low 之 edge 認為 active) TMR0In 計時 / 計數器 0 (Timer/Event Counter 0) 之輸入腳為史密特 觸發輸入 TMR1In 計時 / 計數器 1 (Timer/Event Counter 1) 之輸入腳為史密特 觸發輸入

11. Function Description Execution Flow –The system clock is derived from either a crystal or an RC oscillator –One instruction cycle consists of four system clocks –The controller uses two-stage pipeline architecture Instruction fetch Execution If the instructions are not continued in the ROM, the instruction will consume 2 instruction cycle, otherwise most of instruction only require 1 instruction cycle

12. Execution Timing

13. Program Counter – PC –Control the sequence of the instruction execution –The lower byte of the PC (PCL) is a readable and writeable register (06H) Moving data into the PCL performs a short jump (the destination will be within the current program ROM page, a page is 256 address space) Function Description (cont.)

14. Program Counter, PC

15. Function Description (cont.) Program Memory – ROM –Use to store the program instructions –Can contain data, table –Is 8K*12 bits Special location –Location 000H After chip reset –Location 004H External interrupt subroutine –Location 008H Timer/Event 0 ISR –Location 00CH Timer/Event 1 ISR –Table location

16. Table Location Any location in the program ROM can be used as look- up tables Two instruction is used to take a table look-up –TABRDC [m] Read current page –TABRDL [m] Read last page –The location of the table read is pointed by the register TBLP (07H) –Low-byte of the table is stored in memory [m] –High-byte of the table is stored in register TBLH (08H)

17. Stack register – STACK –Is used to save the contents of the PC only –It has 16-level –At a subroutine call or interrupt acknowledge signal, the contents of the PC are pushed onto the stack –At the end of a subroutine (RET) or an end of interrupt routine (RETI), the PC is restored from stack –If the stack is full and a non-masked interrupt takes place The interrupt request flag will be recorded but the acknowledge signal will be inhibited When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced If stack is full and a “CALL” is subsequently executed –Stack overflow occurs and the first entry will be loss Function Description (cont.)

19. Data memory – RAM –256 * 8 bits –Divide into two functional groups Special function registers General purpose data memory (224*8) –Most of data memory are read/write, but some are read only (ex: TBLH) –All of data memory can be handle with arithmetic, logic, increment, decrement, and rotate operations directly –Each bit in the data memory can be set and reset by “SET [m].i” and “CLR [m].i”

20. Data memory – RAM indirect address register –RAM 記憶體的位址 00H (IAR0) 與 02H(IAR1) 為間接定址暫存器，但實際上並無此真實暫 存器，而是分別與位址 01H 、 03H 之記憶體指 標 (RAM Pointer, MP0 、 MP1) 做間接定址 MOV A, [00H] 後 ， A 的值為 37H – 另外，有下列幾點要注意： 對位址 IAR0 或 IAR1 做間接定址讀取時，取得的值 為 0 。 對位址 IAR0 或 IAR1 以間接定址方式寫入時， CPU 將不會做任何事。

21. Data memory – RAM Accumulator –The data movement between two data memory locations must pass through the accumulator Status register – STATUS –C bit (carry flag) ：當加法運算結果有進位或減法運算結果沒有借位，則此 bit 設 為 1 ，其餘則設為 0 ； –AC bit ( 輔助進位旗標 ) ：當加法運算時，第 4-bit (low nibble) 有半進位或減法運 算第 4-bit 沒有半借位，則此 bit 設為 1 ，其餘則設為 0 ； –Z bit ( 零值旗標 ) ：當算術或邏輯運算結果為 0 時，此 bit 設為 1 ，其餘則設為 0 ； –OV bit ( 溢位旗標 ) ：當算術運算時，有進位到最高位元 (MSB) ，但沒有由最高位 元再進位或無進位到最高位元 (MSB) ，但有由最高位元進位出去時，此溢位旗 標設為 1 ，其餘則設為 0 ； –PDF bit ( 省電旗標 ) ：當執行 HALT 指令時，此位元設為 1 ； –TO bit ( 當 watchdog timer timeout 時，此位元設為 1 。

22. 中斷 (Interrupt) One external interrupt) 、 Two internal Timer/Event counter interrupt) Interrupt control register(INTC, 0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags Register Bit No. Label Function INTC (0BH) 0EMI Controls the master (global) interrupt (1=enabled; 0=disabled) 1EEI Controls the external interrupt (1=enabled; 0=disabled) 2ET0I Controls the Timer/Event Counter0 interrupt (1=enabled; 0=disabled) 3ET1I Controls the Timer/Event Counter1 interrupt (1=enabled; 0=disabled) 4EIF External interrupt request flag (1=active; 0=inactive) 5T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) 6T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) 7--- Unused bit, read as “0”

23. Interrupt 當中斷發生且跳到相對之中斷服務程式 (ISR) 時 – 晶片自動將 INTC 之 EMI-bit 清為 0 ，暫停所有中斷服務， – 直到結束 ISR 程式，返回一般程式時，系統亦自動將 enable EMI-bit 如此可避免 interrupt nesting 情況。 若在 disable EMI 情況下有其它中斷進來時，僅會設定相對中斷要求旗標，直到 enable EMI 後再執行相對之中斷服務。 若某些情況下允許 interrupt nesting ，則可用人為方式將 EMI-bit enable 。 除了 EMI-bit disable 可暫停所有中斷服務外，若 stack full 亦會暫停中斷服務，僅 設定其相對之中斷要求旗標。 另外，所有中斷來源皆有 wake-up 功能。 當系統可對某個中斷來源提供服務時，目前的 PC 會被 push 到 stack ，並根據中斷 來源，晶片會跳到相對 ROM 位址。 No.Interrupt SourcePriorityVector aExternal Interrupt104H bTimer/Event Counter0 Overflow208H cTimer/Event Counter1 Overflow30CH

25. Oscillator configuration 3 oscillator circuit in the microcontroller for system clocks –External RC oscillator –External crystal oscillator –Internal RC oscillator The HALT mode stops the system oscillator If the internal RC oscillator is used, the OSC1 and OSC2 can be selected as 32768Hz crystal oscillator (RTC OSC ) –This is call internal RC + RTC mode

26. 系統頻率來源 (system clock) ROM Code Option Crystal Oscillator (Max 8MHz) External RC Oscillator Internal RC oscillator fs, System Clock ÷4 Instruction Cycle

27. Watchdog Timer, WDT WDT clock source has (which is determined by ROM code option) –Dedicated internal RC oscillator (WDT oscillator, about 72us/clock) –RTC clock –Instruction clock Use to prevent a software malfunction or jump to an unknown location The watchdog timer can be disabled by ROM code option The RTC clock only is enabled in the internal RC+RTC mode 72 us 72 us/256 = 18.6 ms System clock may be disabled by HALT

28. 有三種情況可將看門看計數器的內容清除： – 外部 reset external reset –software instruction CLR WDT Or “CLR WDT1” and “CLR WDT2” –HALT instruction If WDT overflow –Under normal operation the “chip reset” is executed –In HALT mode, a “warm reset” is executed. (only PC and SP are reset to zero)

29. Power down operation - HALT entered by the “HALT” instruction –System clock is turn off –The contents of the on chip RAM and registers remain unchanged –WDT and WDT prescaler will be cleared and recounted again –All off the I/O ports maintain their original status –The PD flag is set and the TO flag is cleared How to leave the HALT mode –External reset –An interrupt If related interrupt is disabled or the interrupt is enable but the stack is full  resume at the next instruction If the interrupt is enabled and the stack is not full  regular interrupt response takes place If an interrupt request flag is set ot “1” before entering the HALT mode, the wake- up function of the related interrupt will be disabled –External falling edge signal on port A (the input pins of port A are selected to wake-up the device by option) Wake-up in the next instruction –WDT overflow (PD and TO is set  warn reset) PC and SP is reseted Once a wake-up event occurs, it takes 1024 system clock to resume normal operation

30. Reset A system reset will occur in the following three ways –RES# pin to reset during normal operation –RES# pin to reset during HALT –WDT time-out during normal operation –WDT time-out during HALT To do a “warm reset”  only reset the PC and SP Programmer uses the TO and PD to distinguish which reset condition is occurred

31. Reset (con’t) To guarantee the system oscillator is started and stabilized –SST (system start-up timer) is provided an extra- delay of 1024 system clock pulses when the system reset occurs

32. Reset (con’t) The function unit chip rest status

33. Timer/Event Counter There are two 16-bit timer/event counters ( 計時 / 計數 器,TMR0, TMR1) –Three clock sources for TMR0/TMR1 Instruction clock cycle f RTC (enable only RC+RTC mode) External signal input (TMR0 pin and TMR1 pin) – external signal input allows user to Count external events Measure time intervals or pulse widths or generate an accurate time base. –Three registers related to the Timer/Event Counter 0/1 TMR0H, TMR0L, TMR0C / TMR1H, TMR1L, TMR1C Write data to TMR0L only write to internal lower-order byte buffer Write data to TMR0H will transfer the specified data and the contents of the lower-order byte buffer to TMR0H and TMR0L preload registers Reading TMR0H will latch the contents of TMR0H and TMR0L counters to the destination and the lower-order byte buffer, respectively Reading TMR0L will read the contents of the lower-order byte buffer TMR0C is the Timer/Event Counter 0 control registe.

35. Timer/Event Counter TM0, TM1 define the operation mode –Event count mode (external clock) Clock source comes from TMR0 pin –Timer mode (internal clock) Clock source comes from f sys/4 or RTC (decision by ROM option) –Pulse width measurement mode Count the high or low level duration of the external signal TMR0 pin (decision by TE-bit of TMR0C) The counting frequency is based on the f sys/4 or RTC (decision by ROM option) In the event or timer mode, the counter will count from the current contents in the counter to FFFFH. –Once overflow occurs, the counter is reloaded from the preload register and generate interrupt request flag In the high/low pulse width measurement mode and TON and TE bit are set to 1, the counter will begin counting when the TMR0 pin in the transient from high to low level –The counter will stop when the TMR0 pin returns to the original level and reset the TON The overflow of the timer/event counter is one of the wake-up source Write data to the preload register will also reload that data to the timer/event counter.

36. Input/output ports 56 bidirectional input/output lines –PA to PG which are mapped to the data memory of [12h][14h][16h][18h][1Ah][1Ch], and [1Eh] –For input operation, these pots are non-latching. MOV A,[m] –For output operation, all data are latched and remain unchanged until the output data are rewritten. –Each port has its own control register PAC[13h], PBC[15h], PCC[17h], PDC[19h], PEC[1Bh], PFC[1Dh], and PGC[1Fh] To function as an input, the coresponding latch of the control register must write “1” –Each bit of these input/output latch latches can be set or cleared by “SET [m].i –Each line of port A has the capability of waking-up the device –All of I/O lines has a pull-high ROM option

38. ROM Code option All of the ROM code options must be defined to ensure proper system functioning