1. GUIDO VOLPI – UNIVERSITY DI PISA FTK-IAPP Mid-Term Review 07/10/2014 - Brussels

2. Personal Information I Joined FTK-IAPP in October 2013 Experimental Physicists with experience in data analysis and trigger PhD in Physics in 2008 at University of Siena Rare hadronic decays of B hadrons at CDF Initial design of FTK with responsibility on simulation Higgs analysis at ATLAS Previously awarded of a 3-year Marie-Curie IOF Fellow (ARTLHCFE) from 10/2010-10/2013 24 months outgoing phase at University of Chicago 12 Months returning phase at CERN 07/10/2014 - BrusselsFTK - IAPP Midterm Review 2

3. Contribution to the WP4 Definition of the code required for the AM tests Introducing new format satisfying the HW requirements for the AM Update and validation of the chain used to produce pattern bank and fit constants Update and validation of the AM emulation Coordination of the FTK emulation for the collaboration Supervising the evolution of the FTK emulation software, with responsibility and coordination and multiple aspects of the emulation Full simulation, detailed HW emulation and test vectors generation, online monitoring planning, fast simulation Contact with the ATLAS software group to follow the evolution of the experiment simulation software Transfer of FTK simulation knowledge 07/10/2014 - BrusselsFTK - IAPP Midterm Review 3

4. The FTK emulation framework The FTK processor functionalities are fully described by a complete emulation framework All the algorithms are described All the internal parameters can be changed Different algorithms can be introduced and tested The framework can be used for electronic design and physics study Continuous effort in maintaining the code updated Maintaining the code in sync with the HW development Maintaining the code coherent with the ATLAS changes 07/10/2014 - BrusselsFTK - IAPP Midterm Review 4 Raw silicon hits Clustering Data distribution Pattern Matching Track fitting FTK tracks

5. Test vector generation updates and requirements The description of all the algorithms has been improved Data formats and workflow have been changed to reproduce more strictly the real algorithm implementation of the different boards The changes have already involved most of the FTK components The generation of the test vectors for the AM boards required changes in many fundamental aspects The fundamental unit of the FTK pattern matching, the super-strip (SS), has been redefined A mapping of ATLAS detector for the hardware has been finalized The training procedures used to generate patterns and the other elements have been completely revisited The pattern bank and the other configuration elements can be directly used by the hardware Pattern matching and other parts updated to exploit the new format Test vector generation doesn’t degrade the performance of the emulation in term of CPU used to emulate the events 07/10/2014 - BrusselsFTK - IAPP Midterm Review 5

6. New SS definition New SS definition designed to use a limited number of bits Previous definition was using too many bits Didn’t allow direct emulation of the DC feature of the AM chip SS described as a sequence of fields in a bitmask Two main components: module address and hit position in the module Clean and ordered description that allows a more natural description in the firmware Can scale if the number of modules changes Elements of the SS word can be easily calculated through simple algebra or using LUT The new format naturally allows to emulate the DC feature Removing a limitation of the previous format, with impact on the emulation structure and ability to produce test-vectors 07/10/2014 - BrusselsFTK - IAPP Midterm Review 6 SS (no DC) Silicon Module SS (1 DC)

7. 07/10/2014 - BrusselsFTK - IAPP Midterm Review 7... 4601 519 820 a8d 22b 1b 1a 1d 16 2 4602 519 833 a87 224 14 14 17 12 2 4603 519 833 a9c 221 f e f b 2 4604 519 833 a9d 225 16 17 18 17 2 4605 519 834 a88 226 17 18 1a 17 2 4606 519 834 a9e 223 11 e e 8 2 4607 519 834 a9e 223 11 f 10 a 2 4608 519 834 a9e 224 13 12 14 f 2 4609 519 834 a9f 227 18 19 1b 19 2 4610 519 834 a9f 228 19 1a 1b 1a 2 4611 519 835 aa0 225 12 e f 7 2 4612 519 835 aa0 225 12 e 10 8 2 … SSs Pattern IDFit Constants *** Roads: *** ROAD 2332 30 1845414 1742786 3904 ; 7: 11011111 ; flags=[0,0,0(-1,-1)] ROAD 2331 30 1564496 3040728 3904 ; 7: 11111011 ; flags=[0,0,0(-1,-1)] ROAD 2330 30 384724 273916 6032 ; 7: 11011111 ; flags=[0,0,0(-1,-1)] ROAD 2329 30 357750 60075 4588 ; 7: 11110111 ; flags=[0,0,0(-1,-1)] ROAD 2328 30 3836355 3786427 1968 ; 7: 11111011 ; flags=[0,0,0(-1,-1)] ROAD 2327 30 3660296 3568824 3908 ; 7: 11101111 ; flags=[0,0,0(-1,-1)] ROAD 2326 30 3512283 3345783 2448 ; 7: 11111011 ; flags=[0,0,0(-1,-1)] ROAD 2325 30 3302433 2981237 1068 ; 7: 11110111 ; flags=[0,0,0(-1,-1)] Road ID Pattern Fit constantsMatch status

8. Trainings and Conferences HiPEAC opportunity training Horizon 2020 projects training PRISMA training VHDL School Presentation at TIPP 2014 “Associative Memory computing power and its simulation” Presentation at HiPEAC conference “The Fast TracKer Emulation, a Highly Flexible Software Project for System Design and Performance Evaluation” 07/10/2014 - BrusselsFTK - IAPP Midterm Review 8

9. Conclusions The generation of the test vector for the AM board has been introduced in the FTK emulation and training procedure Substantial changes done in the software package Great support from the Pisa group High responsibility and visibility role within the FTK collaboration High visibility within the ATLAS experiment community Achieved important skills in the development of large electronics project and the definition of the algorithms Improved my leadership and coordination skills Possibility to often present my work within the ATLAS community and at international conferences 07/10/2014 - BrusselsFTK - IAPP Midterm Review 9