1. 1 Paper reading A New Approach to FFT Processor Speaker: 吳紋浩 第六組 洪聖揚 吳紋浩 Adviser: Prof. Andy Wu Mentor: 陳圓覺

2. 2 Outline  FFT Concepts  Radix-2 2 Algorithm  R2 2 SDF Architecture  Our simulation  Conclusion

3. 3 DFT  DFT of size N ： Define as a twiddle factor of  Matrix of DFT calculation ： (ex. n=8) Repeated &trivial!

4. 4 Apply FFT Algorithm  To improve performance  Use DIF or DIT FFT algorithms to simplify the calculation process  Reduction ： (i) twiddle factor decomposition (ii) trivial twiddle factors ： ex

5. 5 Pipeline FFT Processors  Characteristic: non-stop processing as data sequence passing the processor  Types of pipeline FFT structures:  (i)SDF (single-path delay feedback)  (ii)MDC (Multi-path Delay Commutator)  (iii)SDC (Single-path Delay Commutator) R2SDF R4SDF R2MDC R4MDC R4SDC

6. 6 Observation  Single delay Feedback: More efficiency  Radix-4 Algorithm : higher multiplier utilization  Radix-2 Algorithm : Simpler butterflies  Radix2 2 SDF: Meets all requirements

7. 7 Simplify DFT  Form:  After reduction: Decompose

8. 8 Use Butterfly Structure  Calculate the trivial factors first in eqn.(3)&(4) ：  Use butterfly structure to represent these function

9. 9 Butterfly with decomposed twiddle factors

10. 10 Flow Charts of Algorithm  Still need a set of 4 DFTs of length N/4 to get X(k)  In DFT, we also reuse BFI and BFII structures  Multiply the reused non-trivial twiddle factors behind BFII ： reuse

11. 11 The function of BF I (1)  First N/2 cycles, the BF I is idle and stores data in the N/2 shift registers  Next N/2 cycles, the BFII computes a 2-point DFT with coming data and data in the shift registers

12. 12 The function of BF I (2)  The butterfly computation  Output Z 1 (n) is sent to BFII  Output Z 1 (n+N/2) is back to register for next N/2 butterfly computations BF I N/2 N/4 BF II st

13. 13 The second butterfly BFII’s structure  With N/4 shift registers  A trivial twiddle factor multiplier is built-in  Apply (-j) by real- imaginary swapping and +/- operation with two bit control signal (s’t) BF II N/4 t s

14. 14 The function of BF II  First N/4 cycles, the BF I is idle and store data in the N/4 shift registers  Next N/4 cycles the BFII computes a 2-point DFT with coming data and data in the N/4 shift registers  When the last ¼ period, BF II multiply (–j) in butterfly computations

15. 15 The role of the log 2 N bit binary counter  a synchronization controller gives signal s, t  address counter for twiddle factors ……..10 st

16. 16 Simulation  Use MATLAB compile  BFI 、 BFII as module  For loop as counter BF I N/2 N/4 BF II st Out of BFI Out of BFII Input ： (1)data input (2)Out of BFI (3)Register Output ： (1)Output of BFI (2)Output of BFII (3)Output as Register input Data input Register Function ： BFI BFII Control by for loop

17. 17 Result  Use fft function in MATLAB for verification

18. 18 Comparison of different pipeline FFT hardware requirement Multiplier #Adder #Memory sizecontrol R2MD C simple R2SDFsimple R4SDFmedium R SDFsimple R2SDF R4SDF R2MDC R2 2 SDF

19. 19 Conclusion  Algorithm (i). Hardware oriented (ii). Multiplicative complexity as Radix-4 but Retain Radix-2 butterfly structures  Architecture (i). Minimum of hardware requirement (ii). High efficiency (75% utility) (iii). Easy to control