1. On Reliable Modular Testing with Vulnerable Test Access Mechanisms Lin Huang, Feng Yuan and Qiang Xu

2. Purpose Is on-chip data transmission reliable? What is the solution?  Correction  Retransmission  Hybrid schemes normal functional mode They are helpful in normal functional mode modular testing However, how about modular testing? Cross talk IR drop and even alpha particle hits … Yield loss

3. Agenda Introduction to Modular Testing Test Data Transmission “Error-Free” Assumption Impact of Fault-Tolerant Schemes The Proposed Solution  “Jitter-Aware” Test Wrapper Design  “Jitter-Transparent” ATE Interface Design Experimental Results Conclusion

4. Introduction to Modular Testing “Divide and conquer” manner  test wrapper  test access mechanisms (TAMs)  ATE Interface basic TAM designs classification  dedicated bus-based access scheme  functional access scheme

5. Reuse On-Chip Network as TAM

6. “Error-Free” Assumption is Questionable Existing work assumes test data transmission to be error-free It is questionable when at-speed functional interconnects are reused as TAMs

7. Fault Tolerance Schemes Retransmission and hybrid schemes are mainstream techniques to achieve fault-tolerant communication Retransmission brings problems  Test traffic jitter  Test bandwidth mismatch

8. The Impact of Retransmission Scheme

9. The Significance of These Problems Given the number of flits in the entire test data volume, the flit error rate, the potential yield loss can be expressed as When and flit size is 32 bits, the test yield loss for the chip containing 21.5M gates [1] is [1] C. Barnhart et al, Extending OPMISR Beyond 10x Scan Test Efficiency. IEEE Design & Test of Computers, 19(5):65-73, Sep.-Oct. 2002 11.47% !

10. Buffer-Only Solution Given the flit injection rate is 0.1 flits per cycle and the extra delay caused by one retransmission is 40 cycles The1 st retransmission The2 nd retransmission 5 reserved flits1 Shortage of reserved flits

11. “Jitter-Aware” Test Wrapper Design Two extra states:  HALT IN  HALT OUT CAPTRUE SHIFT HALT OUT HALT IN Output Blocked Input Blocked IEEE 1500 Finite State Machine

12. Wrapper Architecture

13. Control Logic of Test Wrapper

14. “Jitter-Transparent” ATE Interface If the ATE operate in a stream mode … Minimum buffer size: that is able to tolerate the extra delay caused by one retransmission Given the flit error rate and the number of flits, the test yield loss can be computed as follows: Without Buffer:

15. “Jitter-Transparent” ATE Interface We propose to divide the entire input test data flow into segments and insert a small section of “don’t-care” bits Data transmission direction

16. Test Yield Improvement Given the flit error rate, the number of flits, and the number of segments, the test yield loss can be computed as follows: Without Buffer: With Minimum Buffer Size:

17. Experimental Setup Commercial 90nm CMOS technology Area overhead  838 two-input NAND equivalent gates An industrial circuit [2]  Number of gates: 2.6M  Number of scan cells: 274K  Compressed scan test data volume: 106M System parameters  Flit injection rate: 0.25 flit per cycle  Flit size: 32 bits  Retransmission delay: 40 cycles [2] C. Barnhart et al, OPMISR: The Foundation for Compressed ATPG Vectors. In Proc. IEEE International Test Conference, pp. 748-757, Nov. 2001

18. Test Yield Loss for a Core with 2.6M Gates Yield Loss: 4.41%Yield Loss: 0.05% Cost: Testing Time Penalty: 0.15% Yield Loss: 28.20% Flit Error Rate: 10 -7

19. Proposed Technique vs. Buffer-Only Solution λ Yield Loss ≤ 1%Yield Loss ≤ 0.5% n b (flits)n p (flits)ΔTpΔTp n b (flits)n p (flits)ΔTpΔTp 1x10 -8 20 0.0003%20 0.0003% 5x10 -8 40200.0006%40200.0009% 1x10 -7 40200.0018%40200.0033% 5x10 -7 100200.0411%120200.0824% 1x10 -6 160200.1642%180200.3297% λ: Flit error rate n b : Buffer size for buffer-only solution n p : Buffer size for the proposed design ΔT p : Testing time extension ratio of the proposed design

20. Conclusion The “error-free” assumption of existing work is questionable Fault-tolerant schemes may lead to traffic jitter and variable test bandwidth “jitter-aware” test wrapper “jitter-transparent” ATE interface We propose a “jitter-aware” test wrapper and an on-chip “jitter-transparent” ATE interface to achieve reliable modular testing Experimental results demonstrate the effectiveness

21. Thank you !

22. Timing Diagram of Test Wrapper