1. Submitted by A.BHAVYA (08321A1012) R.PRATHIMA(08321A1030) A.SWETHA(08321A1057 ) Internal guide External guide G.VAMSI KRISHNA P.NEERAJA Assistant professor Scientist ‘C’ EIE,BRECW RCI,DRDO HYDERABAD.HYDERABAD.

2.  The emergence of Field Programmable Gate Arrays (FPGAs) with embedded processors and significant progress in their development tools have contributed to the realization of high performance interfaces, run simultaneously in the FPGA logic. Important application areas of FPGAs are Data acquisition systems.  Data acquisition is the process of sampling signals that measure real world physical conditions and converting the resulting samples into digital numeric values that can be manipulated by a computer.

3.  To determine the limitations that a fluctuating environment places on target detection methods, a data acquisition system is being developed.  The data acquisition system consists of multi-channel, high-speed A/D and FPGA technology to control it.  The basic aim of this project is to route various channels to which the sensors are connected to the Analog to Digital Converter (ADC) through multiplexers.

4. The components of data acquisition systems include:  Sensors that convert physical parameters to electrical signals.  Signal conditioning circuitry to convert sensor signals into a form that can be converted to digital values.  Analog-to-digital converters (ADC), which convert conditioned sensor signals to digital values.  An ADC is one of the key components in Data acquisition systems as it governs the speed and performance of the systems.

5. SENSOR O/P(DIFF) SENSOR O/P (S.E) FPGA ADC S.E MUX BUFFER DIFF MUX OPTO COUP LERS

6. FPGA  FPGA is introduced in 1985 by Xilinx.  Field programmable gate array, a type of logic chip that can be programmed. An FPGA is similar to a PLD, but whereas PLDs are generally limited to hundreds of gates, FPGAs support thousands of gates.  Fpga consists of logic blocks, routing matrix, I/O blocks, memory, advanced features.

10. OPTOCOUPLER  It transfer electrical signals to provide coupling.  Called as optoisolators,photocoupler. MULTIPLEXERS  A device that combines multiple input signals(information channel) into an aggregate signal (common channel) for transmission.  2 types (differential and single ended).  ADG526A (S.E),ADG527A(diff).

11.  Multiplexing can be defined as a technique that allows simultaneous transmission of multiple signals across a single data link.

12.  The ADG526A switches one of 16 inputs to a common output, depending on the state of four binary addresses and an enable input.  The ADG527A switches one of eight differential inputs to a common differential output, depending on the state of three binary addresses and an enable input.  These multiplexers also feature high switching speeds and low RON.

13. ADG 526A ADG 527A

14.  Single- or Dual-Supply Specifications with a Wide Tolerance.  can be easily interfaced with microprocessors.  Low Leakage. Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits.  Extended Signal Range.  Break-Before-Make Switching.

15. Features  It is a16 bit ADC.  High speed serial interface.  Power dissipation is 100mw (max).  Fast 16-Bit ADC  100 kSPS Throughput Rate—AD977  200 kSPS Throughput Rate—AD977A  Single 5 V Supply Operation  Unipolar; 0 V–10 V, 0 V–5 V and 0 V–4 V

16.  Bipolar; _10 V, _5 V and _3.3 V  Choice of External or Internal 2.5 V Reference  20-Lead Skinny DIP or SOIC Package  28-Lead Skinny SSOP Package Specifications  On chip clock.  I/p range is 0-5v.  AD977A chip is used.

19.  The project deals with designing a Multi Channel Data Acquisition System. The design basically consists of three parts:  FIFO design  Control Logic  Shift Register followed by another FIFO design  The output of the second multiplexer is then given to the ADC. The required channel is routed to the ADC by latching in suitable select lines to the multiplexers.  The On-Board Computer (OBC) gives the channel numbers to the FPGA which are stored in the first FIFO. The channel numbers are stored in the FIFO till it is full.

20.  The read signal is given to fifo then channel number is decoded by the control logic.  The control signals and select lines are given to the multiplexers for channel selection and routing to the ADC.  Then gives convert signal to the ADC for converting the received sample.  The serial data from the ADC is then deserialized to a shift register.  The digital data stored in the second FIFO is again read by the OBC.  The following figure describes the main blocks in the design.

22.  A finite state machine (FSM) or finite state automaton or simply a state machine, is a model of behaviour composed of a finite number of states, transitions between those states, and actions.  Finite state machines represent a very powerful way of describing and implementing the control logic for applications.  And they are powerful because they can be used to generate code

23. Moore machine  The FSM uses only entry actions, i.e., output depends only on the state. The advantage of the Moore model is a simplification of the behaviour. Mealy machine  The FSM uses only input actions, i.e., output depends on input and state. The use of a Mealy FSM leads often to a reduction of the number of states

24.  The next state and output of an FSM is a function of the input and of the current state. IDLE Write channe l STATE 7 Store in FIFO2 STATE 3 rc=1 STATE4 Check for ADC busy STATE6 Sum and avg 4 sample s STATE5 Deseriale serial input From ADC STATE2 Decode Channel no STATE 1 rd=1 Full=1 reset nbusy=1 Count<4

25. Fifo result As shown in the figure when the write signal is given to the FIFO1 the data is written and when read signal is given then the data will be presented at dout. Here the wr_req is given from 16‘h0000 to 16‘h0003 and at the rd_req the data is read

26. Serial to parallel shifter is used to increase the speed of response. Here the serial data 0010011011111111 is given to shift register such that it converts it to parallel as shown in figure

28.  In this figure when processor write signal is applied the data is written and when read signal is applied the read reads the data according to the channel number the selection line of mux is selected.  If fdata_out 7 the only mux2 is enabled thus this data sent to the ADC for conversion. such that r/c remains low for 6ons  when conversion completes r/c becomes high and busy signal becomes low.when data is ready the it is given to shift register later the data is sent to FIFO2.

29. FEATURES  Virtex®-II Pro FPGA with PowerPC® 405 cores  Four switches connected to Virtex-II Pro I/O pins  Five push buttons connected to Virtex-II Pro I/O pins  100 MHz system clock, Provision for user-supplied clock  On-board power supplies  Power-on reset circuitry  PowerPC 405 reset circuitry

30.  This project describes the implementation and integration of hardware and software of a serial ADC in a Virtex-2 pro FPGA with an embedded Power PC 405 processor.  A 16-bit ADC with high speed, low power serial interface will be implemented in VHDL using Xilinx ISE. The hardware and software will be developed and combined using Xilinx EDK.  Xilinx Platform Studio (XPS) will be used to perform synthesis, place and route and obtain the configuration bit-stream. The final configuration bit will be downloaded onto the custom target board using Impact tool and the results will be verified.

31.  Digital to analog converter can be used for implementation of data acquisition system using virtex 2 pro fpga.  The analog data can be converted to digital using analog to digital converter to display on computer. Applications:  In defence.  In missile interface unit.

32. THANK YOU