1. EDAQ for R3B (and related interfaces) November 2011 Ian Lazarus

2. Si Inner Si Middle Si Out er ASIC 120k strips 912 ASICs Si Inner ASIC Si Middle ASIC Si Out er ASIC x6 x12 FPGA enet FPGA enet FPGA enet FPGA enet FPGA enet FPGA enet VacuumAir R3B Slow Control Switch DAQ PC(s) To R3B DAQ 30 FEE cards CALIFA Timestamp & trigger links

3. Si Ladder ASIC FEE Card Number determined by the data rate (depends on shielding) With Au shield-30 cards BUTIS Fan-out NUSTAR Common DAQ R3B input code module Gbit Ethernet fibres ASIC Fibre Ethernet R3B conceptual design for Si tracker FEE and DAQ with estimated data rates fibre links either fibre or HDMI links Slow Control Grey boxes show common NUSTAR elements 100um Gold shield- Max 210 MBytes/sec 100-300kBytes/sec/ASIC, ave 225kBytes/sec/ASIC Total Data Rate: No shield 5.7Gbytes/sec (at least 189 fibres) Gold cone 210Mbytes/sec (at least 7 fibres)

4. PreAmp Shaper TFA Pk Hold Mux ADC 12 bit 1MHz Control Time Stamp Buffer and Serial Readout PreAmp Shaper TFADiscr. Pk Hold x128 R3B Si Tracker ASIC ASIC features: Time Stamp Zero Suppress On chip ADC NO TAC (we have found no ToF requirement) Discr.

7. Topics 1)Data rates- working on the basis that my spreadsheets based on 100um Au foil shield are right (averages, no “hot spots” (2x is OK)) 2)Agreed feed-throughs from detector PCB to readout (2x30) 3)Agreed isolation of signals from detector to/from readout. 4)Agreed with CALIFA about ways to cut data rate by gates and TS exchange (NB this is NOT replacement for gold foil which must protect the front end of the ASIC (preamp, shaper) from pileup.) 5)Readout card design started (Mos)- uTCA? 6)FEE will monitor PT100 and Si leakage current as well as reading data and controlling the ASICs, supplying bias and ASIC power. 7)ASIC daisy chaining and readout protocol (today & next Friday)