1. LFB, LLRF, TFB update Alessandro Drago XIII SuperB General Meeting Isola d’Elba, 5/30-6/4 2010

2. Topics Longitudinal dynamics simulator:  beam + RF + LFB Longitudinal growth rate evaluation Power amplifiers evaluation LLRF update Transverse dynamics simulator Hardware update

3. Feedback design basic points Hardware refresh (to avoid obsolescence) Legacy/diagnostics from the previous feedback systems Unified project for transverse and longitudinal systems Evaluation of feedback impact on ultra-low emittance beams Signal/noise ratio (included crosstalk from other bunches) of the order of ~40 dB System dynamic range of the order of ~75/80 dB

4. Poster presented at IPAC 2010 Kyoto May,2010

6. Data base in SIMUL2 longitudinal simulator are: RF power, 11 HOM in RF cavities, beam paramenters (charge x bunch, harmonic number, #bunches, gap, injection error) and Longitudinal feedback parameters (gain, power, FIR transfer function with coefficients)

7. The longitudinal simulator upgrade MATLAB program have been upgraded and rewritten to make a fast data entry and also to measure growth and damping rate from the raw output data

8. Baseline

10. LER High Current

14. Summary of long. growth rates 4A in 1956 bunches generates at every new charge injection very fast instability Injecting bunch #2 the instability growth rates are faster in the nearby bunches than in the others along the bunch train Bunch #11  178 turns, 0.75 msec Bunch #1225  673 turns, 2.82 msec Bunch #1955  691 turns, 2.93 msec

15. High current case (4A), bunches spaced by 1: lfb needs a total power of 1kW, implemented by four 250W amplifiers feeding one cavity kicker with Rs>500Ohm. This power should be sufficient to control the beam longitudinal dynamics at 4A in LER

16. LLRF - Low Level RF System description (from CDR2 by Sacha Novokhatski) A low-level RF system provides control and feedback for stable multi- bunch high current operation. There are several feedback loops. BLOCK DIAGRAM OF LLRF CIRCUITS

17. LLRF update by the Grenoble Team in the next SuperB General Meeting

18. Transverse model with FPGA code

19. Beam transfer function [transverse resistive wall instability] Grate = modal instability hypothetical growth- rate [from real example: DAFNE or CESR-TA] In DAFNE, the e+ ring fastest measured Grate is ~20 revolution turns Wx = angular betatron tune frequency [2*pi*betatron_tune_fractional_part*rev_freq] G = gain (function of impedances & wakefields, RF_frequency^2, bunch_spacing,…) - in the preliminary phase is put to 1

20. C.S.N.V approves SFEED in Sept/09 Only for the year 2010 2K euro for mission outside Italy 16 k euro for hardware/software and assembly

21. Finally a Virtex-6 FPGA evaluation board is now on sale: Xilinx ML605

22. Finally a Virtex-6 FPGA evaluation board is now on sale Xilinx ML605 – similar to previous project based on Virtex-5 Part number AES-V6DSP-LX240T-G http://www.xilinx.com/products/devkits/AES- V6DSP-LX240T-G.htmhttp://www.xilinx.com/products/devkits/AES- V6DSP-LX240T-G.htm Expensive cost: 2995 $ + VAT cointaining Xilinx ML 605 Development Board including Virtex-6 LX240T FPGA. http://www.xilinx.com/products/devkits/EK-V6- ML605-G.htmhttp://www.xilinx.com/products/devkits/EK-V6- ML605-G.htm Only the board: 1995 $ +VAT.

23. 14 bit ADC / 16 bit DAC ADC (analog input signal): ADS5474 byTexas Instruments, [14-bit, 400 MSPS] http://focus.ti.com/lit/ds/symlink/ads5474.pdf It has 14 differential digital output LVDS on a unique register then better than the previous project that was using 16 digitalc output beacasuse was based on 2 registers ADS5474 has an evaluation board: http://focus.ti.com/lit/ug/slau194a/slau194a.pdf DAC: Maxim MAX5891 http://www.maxim- ic.com/quick_view2.cfm/qv_pk/4622http://www.maxim- ic.com/quick_view2.cfm/qv_pk/4622 16-Bit, 600Msps High-Dynamic Performance DAC with LVDS Inputs and DAC evaluation board: http://datasheets.maxim-ic.com/en/ds/MAX5889EVKIT-MAX5891EVKIT.pdf The evalutation board has 16 differential LVDS input with a single connettor while clock and analog output signal are SMA

24. 14 bit ADC / 16 bit DAC It is necessary to assembly 3 boards designing an interface board connecting all the evaluation boards ( ADC@14bit, FPGA with Virtex-6, DAC@16bit). The software, firmware and gateware for the FPGA board ML 605 should be also designed

25. 14 bit ADC / 16 bit DAC An order for these 3 boards has still NOT signed by LNF top management (I am waiting since more than 1 month) Why???

26. DIMTEL order An order to DIMTEL has made in last January for two longitudinal front end modules and two 12-bit ADC processing unit It is an upgrade from IGP to IGP-12 It is based on Virtex-5 not on Virtex-6 The order is in progress and we are still waiting for the material Material is sold as a black box (no info about code)