1. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso1 Status of front-end electronics for the OPERA Target Tracker LAL Orsay S.BONDIL, J. BOUCROT, J.E.CAMPAGNE, A.CAZES, C. de LA TAILLE, A. LUCOTTE, G. MARTIN- CHASSARD, L. RAUX, J.P. REPELLIN BERN University K.BORER, M.HESS Oscillation Project with Emulsion-tRacking Apparatus

2. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 2 Contents 1.Version 2 chip prototype (Reminder)  Chip characteristics  Measurements (made in collaboration with Bern) 2.Version 3 chip prototype – OPERA-ROC (ReadOut Chip)  Chip characteristics  Measurements (made in collaboration with Bern) 3.Conclusion and perspectives  Comparison: Version 2 vs version 3  Production schedule  Production cost

3. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 3 32 inputs (Ch1-Ch32), trigger output + 1 multiplexed charge output  Variable gain preamplifier : range 1-3, resolution = 4 bits (1, 0.5, 0.25, 0.125)  Fast shaper (t p = 20 ns, G ~ 20) for auto-trigger (1/3 pe)  Slow shaper (t p = 100 ns, G ~ 1) for charge measurement  On chip track & hold and output multiplexer Version 2 prototype front-end chip  Technology: AMS 0.8  m BiCMOS  Chip area : 10 mm 2  Package : QFP100  Power consumption : 250 mW – Submitted in September 2002 – Received in March 2003 – Validated in April 2003

4. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 4 Version 2 chip Tests: summary 32-channel chip (version 2) Preamplifier: Gain correction Input impedance Operational (4 bits): Effective range [0-2.8] 1.5-2k Ohms Auto-Trigger : Fast Shaper t P Fast Shaper Gain Pedestal spread Noise RMS Comparator t P = 20 ns 800mV/pC ( 130 mV/pe) ~ 0.1 pe ~ 1 mV ( ~ 0.01 pe) Operational:  =100 % down to 1/4 pe Charge measurement : Slow Shaper t P Slow Shaper Gain Dynamic range Pedestal spread Noise RMS Cross-talk t P = 100 ns 140 mV/pC ( 22 mV/pe) [0-75] pe ~ 40 mV ( ~1.5 pe) 0.5 mV ( ~0.02 pe) ~ 1% –The version 2 chip performance suits the Target Tracker requirements –Validation procedure is reported in OPERA note 40 1 p.e. = 160 fC @ 10 6

5. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 5 Version 3 chip (Reminder) Version 3 chip – OPERA ROC(ReadOut Chip)  Significant improvements Reduced cross-talk (decreased preamplifier input impedance) Reduced pedestal spread in charge measurement and autotrigger  Main new features included: (tested in a previous test chip: « meccano chip ») New preamplifier architecture with low input impedance and increased gain correction range (on 6 bits) : from 0 to ~ 4 New Fast Shaper structure (differential configuration amplifier) : low offset New Slow Shaper structure (Sallen-Key structure and differential configuration amplifier): low offset Improved Track & Hold based on Widlar structure Register to identify the triggered channel – Submitted in November 2002 – Received in March 2003 – Validated in May 2003  Technology: AMS BiCMOS 0.8  m  Chip area : 10 mm 2  Package : QFP100  Power consumption : 185 mW

6. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 6 i in i out Version 3 chip test: Preamplifier Preamplifier performance  Preamlifier Gain (G=1) : 95 mV/pC (15 mV/pe) (1 pe=160 fC @ 10 6 )  Gain Correction : Operational : 6 bits => 64 levels of corrections (2,1,1/2,1/4,1/8,1/16) Effective range: from 0 to 3.5 (0 to ~ 4 expected) Possibility to switch OFF/ON any individual channel  Noise : < 0.01 pe @ 10 ns and 200 ns  Input Impedance : Z in ~110 Ohms (1.5k-2k Ohms in Version 2) Slow shaper Fast shaper 0.01 pe

7. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 7 Version 3 chip tests: Auto-trigger (I) Fast Shaper :  Fast Shaper Gain: ~ 4.5V/pC (~800 mV/pe)  Fast Shaper Peaking time: t P ~ 15 ns  Noise RMS: ~ 1 mV (~ 0.01 pe) Comparator :  Efficiency:  =100 % down to 1/10 pe (goal: 1/3)  Offset spread: ~  0.02 pe : 2 sources => Fast shaper (main contribution) and Comparator (negligible) Fast Shaper V out vs Q in V out (V) 0.12 p.e. 12 p.e. 1.2 p.e. Gain 2:1 Time (  s)  0.02pe Gain 1 Gain 3

8. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 8 Version 3 chip tests: Auto-trigger (II) Comparator :  Time walk : Δt~15 ns 15 ns Hit Register :  Allows to Identify the triggered channel : Operational Crosstalk sensitive for Q inj >20pe

9. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 9 Version 3 chip tests: Charge measurement (I) Measured Performance:  Dynamic Range: Linearity: < 1% [0-20] pC  [0-125] pe  Slow shaper Gain (G=1): ~125 mV/pC (20 mV/pe)  Slow shaper peaking time: t p ~160 ns Version 2 Version 3 Dynamic range [0-75] pe Dynamic range [0-125] pe Slow Shaper V out vs Q in Time (s)

10. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 10 Version 3 chip tests: Charge measurement (II) Measured Performance:  Track & Hold: Fully Operational : Widlar Structure: OK  Noise RMS : ~ 1.5 mV (0.07 pe)  Pedestal spread :  6 mV ( ~ 0.3 pe) peak-to-peak (~  1 mV expected)  6 mV  20 mV Version 3 Version 2

11. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 11 Channel-to-Channel cross-talk :  2 contributions : Capacitive coupling between neighboring channels: less than 0.3% (low input impedance) Systematic injection in all channels (comes from power supplies): less than 0.5% Trigger-Charge cross-talk  Cross talk Trigger measurements negligible Version 3 chip tests: Cross-talk sampling time  1/100 Neihgboring channels Q inj =1/3 pe

12. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 12 Comparison :Version 2 vs Version 3 185 mW250 mWConsumption QFP 100 Package Range 0-3.5, 6-bit resolution : 0 + (2, 1, 1/2, 1/4, 1/8, 1/16) Z in ~ 110  3 pF alternate Range 1-2.8, 4-bit resolution : 1 + (1, 1/2, 1/4, 1/8, 1/16) Z in ~ 1.5 to 2 k  None Gain correction Input impedance Input for test pulse t P =15 ns 4.5 V/pC (700 mV/pe) ~ 0.03 pe ~ 1 mV (~1/1000 pe) Operational:  =100 % down to 1/10 pe 15 ns Operational t P =20 ns 800 mV/pC (130 mV/pe) ~ 0.1 pe ~ 1 mV ( ~0.01 pe) Operational:  =100 % down to 1/4 pe 15 ns None Fast Shaper t P Fast Shaper Gain Pedestal spread Noise RMS Comparator Time walk Hit register OPERA-ROC (version 3 chip)Version 2 chip [0-12pC] ([0-75pe]) ±20 mV (± 1 pe) ~ 0.5 mV (~0.02 pe) t P =110 ns 140 mV/pC (22 mV/pe) ~1% [0-20pC] ([0-125pe]) ±6 mV (±0.3 pe) ~ 1.5 mV (~0.07 pe) t P =160 ns 125 mV/pC (20 mV/pe) <1% Dynamic range Pedestal spread Noise RMS Slow Shaper t P Slow Shaper Gain Cross-talk 1 p.e. = 160 fC @ 10 6 Preamplifier Auto-trigger Charge measurement

13. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 13 Conclusion: Version 2 vs Version 3  Both versions suit the Target Tracker requirements and are validated  Both versions can be used without any new iteration  But version 3 improves significantely version 2  The chip must to be tested with the Bern Front-end board Prototype –Proposal : OPERA ROC (Version 3) is considered as the baseline chip

14. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 14 Production schedule  Production could start in July 2003  Delivery expected in Orsay in October 2003  Test of the mass-produced chips will take place in Orsay in November 2003: Bench-test set-up has started  Chips available for the collaboration by January 2004

15. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 15 Production cost estimation  Both versions are cost equivalent (same area: ~10mm²)  Silicon : 2800 dies (assuming 80% yield and 200 spares) : 48 k Euros  Package : PQFP-100 : 7 k Euros  Total : 55 k Euros (~ 0.7 Euros per channel)

16. Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso 16 Version 3 chip tests: Auto-trigger (I) Fast Shaper :  Fast Shaper Gain: ~ 4.5V/pC (~800 mV/pe)  Fast Shaper Peaking time: t P ~ 15 ns  Noise RMS: ~ 1 mV (~ 0.01 pe) Comparator :  Efficiency:  =100 % down to 1/10 pe (goal: 1/3)  Offset spread: ~ 0.05 pe : 2 sources => Fast shaper (main contribution) and Comparator (negligible) Fast Shaper V out vs Q in V out (V) 0.12 p.e. 12 p.e. 1.2 p.e. Gain 2:1 Time (  s)