1. 1 Power supply per Fisica delle Alte Energie: problematiche e soluzioni innovative B.Allongue 1, G.Blanchot 1, S.Buso 2, F.Faccio 1, C.Fuentes 1,3, P.Mattavelli 2, S.Michelis 1,4, S.Orlandi 1, G.Spiazzi 2 1 CERN – PH-ESE 2 Dept. Information Engineering, Padova University, Italy 3 UTFSM, Valparaiso, Chile 4 EPFL, Lausanne

2. 2 Outline Present power distribution architectures at LHC experiments Expected power supply requirements for the future LHC upgrade Serial powering Parallel powering: DC-DC converters based solution –DC-DC converter topologies for Point of Load (POL) converters Conclusions

3. 3 Typical low-voltage power distribution in LHC trackers: No on-detector conversion. Low-voltage (2.5-5V) required by electronics provided directly from off-detector. Sense wire necessary for PS to provide correct voltage to electronics. Cables get thinner when approaching the collision point (strict material budget). Patch Panels (passive connectors) PS In view of SLHC: -Scheme not easily scalable to the larger currents expected (see next slides) Present Power Distribution Schemes in Trackers (ATLAS)

4. 4 AC/DCDC/DC PP PP (with “LDO” in some cases) PP Module 0.5-2m 13-15m 100m 1A/channel (analog or digital), round-trip cables, and sense to nearest regulation AC/DC PP Module 0.5-2m100m PP Module 0.5-2m PP Module 0.5-2m DC/DC

5. 5 Example: LAr Calorimeter Power Supply

6. 6 Total power: 3 kW Output voltages: V out1 = +6V – 100A V out2 = +11V – 20A V out3 = +7V – 160A V out4 = +6V – 150A V out5 = +4V – 130A V out6 = -4V – 180A V out7 = +7V – 15A Low Drop-Out (LDO) regulators on board

7. 7 Example: CMS Power Supply Architectures Source: S. Lusin, TWEPP ‘07

8. 8 Why independent powering fails at SLHC ? Don’t get 5 or 10 times more cables in Power efficiency is too low (50% ATLAS SCT  ~15% SLHC) Cable material budget Packaging constraints Source: M. Weber, TWEPP ‘07

9. 9 Example: ATLAS Tracker Detector Read-out hybrid Front-End readout ASIC - I digital ≥ I analog (for instance, current projection for ATLAS Short Strip readout is I analog ~ 20mA, I digital ~ 60-100mA) - 2 power domains: V an =1.2V, V dig =0.9-0.8V (as low as possible) - Clock gating might be used => switching load All ASICs will be manufactured in an advanced CMOS (or BiCMOS) process, 130nm generation or below. Here we consider only CMOS ASICs. Hybrid/Module controller - Ensures communication (data, timing, trigger, etc.) - Digital functions only - It might require I/Os at 2.5V rod/stave controller, optoelectronics components Other than the rod/stave controller, optoelectronics components will also have to be used, requiring an additional power domain (2.5-3V) Detector module Rod/stave Source: S. Michelis, TWEPP ‘07

10. 10 N of layers Min and Max R (cm) Barrel length (cm) N of chips N of hybrids Active power (KW) Load current (KA) SCT barrel430, 5115325,000210011.62.75 (@3.5-4V) SLHC SS layers, barrel 338, 60200173,000860016.2 (@0.9-1.2V) 20.3 (@1.2V) 17.2 (@0.9-1.2V) Example: ATLAS TrackerSummary - 3 Voltages to be provided to minimize power consumption: - 2.5V for optoelectronics and (maybe) control/communication ASICs - 1.2V for analog circuitry in FE ASICs - 0.8-0.9V for digital circuitry in FE ASICs. This domain uses most of the current! - Digital current might be switching in time (to really minimize the power) Power and Current in LHC/SLHC - - Projection based on current estimate for ATLAS upgrade - Only accounting barrel detector, power from Readout ASICs only - SCT is LHC ATLAS Silicon Tracker detector, to be replaced (grossly) by Short Strip layers in present upgrade layout Large current increase (Power on cables = RI 2 ) Large waste of power if V an =V dig =1.2V Source: S. Michelis, TWEPP ‘07

11. 11 Working Environment High magnetic field (up to 4T in CMS, 2T in ATLAS) High level of radiation inside the detectors: –LHC doses probably increased x 5 – 10 so we can extrapolate to hundreds of Mrad in several Tracker location, decreasing to ten(s) in the outer Trackers

12. 12 Power Distribution Schemes Serial Powering (SP) –Shunt regulators Parallel Powering (PP) –Inductor-based switching converters –Switched capacitor converters

13. 13 Serial Powering P c = I m 2 RcP M = nI m V m Efficiency:= Example of efficiency plot vs. number of modules (n) vs. number of modules (n) and supply voltage (V) for I m = 2 A R c = 3 Ω for Serial Powering scheme Powering schemes comparison Source: G. Villani, TWEPP ‘07

14. 14 Shunt Regulation in SP External shunt regulator + external power transistor Constant current source Load Source: G. Villani, TWEPP ‘07

15. 15 Parallel Powering Example of LAr calorimeter power supply niPOL = Non-Isolated Point of Load Converters

16. 16 VIVI Solution without converter: Solution with converter: N V I/N ↓ Power losses on cable = ↑ Power losses on cable = Converter Ratio N Converter 2 V2I2V2I2 R Reduction of Cable Power Losses

17. 17 Conversion stage 2 (ratio 2) - Embedded in controller or readout ASIC - Closely same converter for analog and digital (different current, hence different size of switching transistors): macros (IP blocks) in same technology Conversion stage 1 (ratio 4-5.5) -Vin=10V => high-V technology -Same ASIC development for analog and digital Controller ASICReadout ASICs 10-12V “analog bus” 2.5V “digital bus” 1.8V 0.9V (core) 2.5V (I/O) 0.9V (V dig ) 1.25V (V ana ) 0.9V (V dig ) 1.25V (V ana ) Proposed Power Distribution Scheme for ATLAS Trackers

18. 18 Implementation ExampleRod/stave V bus 2.5V Converter stage 1 Optoelectronics Stave controller 1.25V Converter stage 2 Detector V bus 2.5V 1.8V Converter stage 1 on- hybrid 2 Converter stage2 on-chip Detector 2.5V 1.8V V bus Detector 2.5V 1.8V Converter stage 1 on-stave Detector 2.5V 1.8V 2 Converter stage 2 on-chip

19. 19 Power supply for ATLAS Trackers The high magnetic field calls for coreless conversion stages Low-value air core inductors can be used with switching frequencies in the megahertz region Inductor-less conversion stages can also be used (switched capacitor converters) Switching noise is a big concern Soft-switching is a must!

20. 20 1.Single phase synchronous buck converter ↑ Simple, small number of passive components ↓ Larger output ripple for same C o ↓ RMS current limitation for inductor and output capacitance 2.4 phase interleaved synchronous buck converter ↑ Complete cancellation of output ripple for a conversion ratio of 4 (with small C o ) ↑ Smaller current in each inductor (compatible with available commercial inductors) ↓ Large number of passive components ↓ More complex control circuitry UgUg uouo Q1Q1 Q2Q2 L1L1 CoCo R load UgUg uouo Q1Q1 Q2Q2 L1L1 Q3Q3 Q4Q4 L2L2 Q5Q5 Q6Q6 L3L3 Q7Q7 Q8Q8 L4L4 CoCo Different Converter Topologies (1/3)

21. 21 3.Two phase interleaved synchronous buck converter with integral voltage divider ↑ Complete cancellation of output ripple for a conversion ration of 4 (with small C o ) ↑ Simpler control and smaller number of passive components than 4 phase interleaved ↓ More components than the single-phase synchronous buck 4.Multi-resonant buck converter ↑ Very small switching losses (zero voltage and zero current switching) ↓ To achieve resonance:  Current waveforms have high RMS value => large conduction losses => lower efficiency  Voltage waveforms have high peaks, possibly stressing the technology beyond max V dd ↓ Different loads require complete re-tuning of converter parameters i L1 i L2 L2L2 L1L1 S2S2 S4S4 S1S1 S3S3 UgUg uouo RoRo CoCo C1C1 + + i C1 u C1 Different Converter Topologies (2/3)

22. 22 5.switched capacitor voltage divider ↑ rather simple, limited number of passive components ↑ lack of inductor => good for radiated noise and for compact design ↓ No regulation of the output voltage, only integer division of the input voltage ↓ Efficiency decreases with conversion ratio (larger number of switches) ↑ Good solution for ratio = 2, for which high efficiency can be achieved Different Converter Topologies (3/3)

23. 23 Single-phase Synchronous Buck Converter Principle of operation i S1 iLiL L S2S2 S1S1 UgUg uouo RoRo CoCo + i S2 The 2°order L-C o filter removes the switching frequency harmonics, making the output voltage DC component dominant t t 0 u DS2 UgUg

24. 24 Single-phase Synchronous Buck Converter Hp: constant voltages Inductor flux balance: t t iLiL t i S1 t 0 i S2 i S1 iLiL L S2S2 S1S1 UgUg uouo RoRo CoCo + i S2 uLuL

25. 25 Single-phase Synchronous Buck Converter Quasi-square wave operation iLiL L S2S2 S1S1 UgUg uouo RoRo CoCo + C o2 C o1 uxux u DS1 T dead UgUg u DS2 S 1 = S 2 = off D 1 = on UgUg Zero Voltage Switching turn on t t iLiL t i S1 t i S2 0 High current ripple

26. 26 Multiphase Interleaved Buck Converters LC S L1 S H1 L S L2 S H2 L S L3 S H3 - + ugugugug uouououo Reduced current level per phaseReduced current level per phase Reduced output current rippleReduced output current ripple Reduced input current rippleReduced input current ripple Increased bandwidth (F eq =N F sw )Increased bandwidth (F eq =N F sw ) N = phase number Same drive signal but phase shifted by T sw /N

27. 27 Multi-Phase Interleaved Converters Ripple reduction on output filter i L1 i L2 i Ltot I o /2 IoIo F sw 2·F sw L C S L1 S H1 L S L2 S H2 - + ugugugug uouououo i L1 i L2 i Ltot Example: 2 phases

28. 28 Output Current Ripple Cancellation D=0.5 for the best cancellation effect Two phases Four phases D=0.25, 0.5, 0.75 for the best cancellation effect 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 00.10.20.30.40.50.60.70.80.91 Duty cycle Ripple Ratio 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 00.10.20.30.40.50.60.70.80.91 Duty cycle Ripple Ratio V o =1.3 V 12 V5 V 12 V5 V Input voltage

29. 29 Multi-Phase Interleaved Converters i L1 i L2 igig I o /2 F sw i s1 i s2 Ripple reduction on input current 2·F sw I o /2 L C S L1 S H1 L S L2 S H2 - + ugugugug uouououo i L1 i L2 i Ltot i s1 i s2 igig

30. 30 Multi-resonant buck converter Example: Input voltage:U g = 12V Output voltage:U o = 3V Output current: I o = 3A Switching frequency: f S = 6.4MHz Resonant inductance: L r = 100nH Switch capacitance: C S = 3nF Diode capacitance: C D = 9nF uSuS uDuD irir iFiF

31. 31 Two-Phase Interleaved Buck with Voltage Divider S1S1 S2S2 S3S3 S4S4 L1L1 CoCo R C1C1 L2L2 U in UoUo + - U C1 + - i2i2 i1i1

32. 32 Two-Phase Interleaved Buck with Voltage Divider t t t i L2 t i L1 i C1 i L1 +i L2 t t 0 i L2 -i L1 t t t i L2 t i L1 i C1 i L1 +i L2 t t 0 i L2 -i L1 D<0.5D>0.5

33. 33 Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 i L1 i L2 L2L2 L1L1 S2S2 S4S4 S1S1 S3S3 U in uouo RoRo CoCo C1C1 + + i C1 u C1 t t t i L2 t i L1 i C1 i L1 +i L2 t t 0 i L2 -i L1

34. 34 Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 i L1 i L2 L2L2 L1L1 S2S2 S4S4 S1S1 S3S3 U in uouo RoRo CoCo C1C1 + + i C1 u C1 t t t i L2 t i L1 i C1 i L1 +i L2 t t 0 i L2 -i L1

35. 35 Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 t t t i L2 t i L1 i C1 i L1 +i L2 t t 0 i L2 -i L1 i L1 i L2 L2L2 L1L1 S2S2 S4S4 S1S1 S3S3 U in uouo RoRo CoCo C1C1 + + i C1 u C1

36. 36 Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 i L1 i L2 L2L2 L1L1 S2S2 S4S4 S1S1 S3S3 U in uouo RoRo CoCo C1C1 + + i C1 u C1 t t t i L2 t i L1 i C1 i L1 +i L2 t t 0 i L2 -i L1

37. 37 Steady-state analysis (D < 0.5) Inductor flux balance: Capacitor charge balance:

38. 38 Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 “Natural” current sharing Optimal ripple cancellation for overall voltage conversion ratio equal to ¼ Reduced switch voltage stress (one half of input voltage)

39. 39 Two-Phase Interleaved Buck with Voltage Divider: D > 0.5 Unequal average currents in the two phases Increased switch voltage stress (equal to the input voltage)

40. 40 Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 D=0.37 i L2 i L1 i L1 +i L2 0 i C1 0

41. 41 Two-Phase Interleaved Buck with Voltage Divider: D > 0.5 D=0.63 i L2 i L1 i L1 +i L2 0 i C1 0

42. 42 + vxvx VgVg C1C1 C2C2 CxCx IoIo ixix igig + + vovo i1i1 i2i2 R Switched-Capacitor Voltage Divider + Q1Q1 vxvx Load VgVg Q2Q2 Q3Q3 Q4Q4 C1C1 C2C2 CxCx IoIo ixix igig + + vovo + vxvx VgVg C1C1 C2C2 CxCx IoIo ixix igig + + vovo i1i1 i2i2 R Topology corresponding to Q 2, Q 4 = “on”; Q 1, Q 3 = “off” Topology corresponding to Q 1, Q 3 = “on”; Q 2, Q 4 = “off” R = 2R DSon +R ESRx C 1 = C 2 = C

43. 43 SCVD: Steady-State Analysis  Input voltage:V g = 3V  Output current: I o = 0.1A  Switching frequency: f S = 200kHz  MOSFET on resistance: R DSon = 100m   Filter capacitors: C = 200nF  Charge transfer capacitor: C x = 10  F vxvx vovo igig ixix V g /2

44. 44 SCVD: Steady-State Analysis Converter efficiency as a function of output current total parasitic resistance R = 2xR DSon for four different output current values: I o = 0.1 A (red curve); I o = 0.2 A (blue curve); I o = 0.3 A (green curve); I o = 0.4 A (magenta curve) (C = 200nF, C x = 10  F)

45. 45 2PIB-VD: Experimental Results at f s = 1MHz Input voltage: U g = 12 V Output voltage: U o = 2.5 V Nominal output power: P o = 7.5W Nominal output current: I o = 3A C in = 100nF + 10  FC o = 2x47nF + 4x2.2  F C 1 = 2x220nF (1206) L 1 = 353nH – 90m  L 2 = 342nH – 86m  S 1,4 = IRF8915

46. 46 2PIB-VD: Experimental Results at f s = 1MHz Converter’s main waveforms at nominal power: S 3 logical driving signal (Blue); output voltage ripple (yellow); S 3 Drain-to-Source voltage (red) i L1 i L2 L2L2 L1L1 S2S2 S4S4 S1S1 S3S3 UgUg uouo RoRo CoCo C1C1 + + i C1 u C1

47. 47 Single Buck Converter: Experimental Results at f s = 1MHz C in = 100nF + 10  FC o = 2x47nF + 2x47  F + 2x10  F L = 222nH – 64m  (12L Coilcraft) Q 1,2 = 2xIRF8915 Input voltage: U g = 12 V Output voltage: U o = 2.5 V Nominal output power: P o = 7.5W Nominal output current: I o = 3A Parallel-connected switches Lower Inductance value

48. 48 Single Buck Converter: Experimental Results at f s = 1MHz Converter’s main waveforms at nominal power: S 1 logical driving signal (Blue); output voltage ripple (yellow); S 3 Drain-to-Source voltage (red) Effect of output cap ESR Quasi-square wave operation

49. 49 Efficiency Comparison at f s = 1MHz C 1 = 2x220nF C 1 = 2x470nF Coilcraft L Home-made L Home-made L: 0.84mm wire diameter (L = 220nH, 50m  ) wound on a plastic support (  = 4.38mm)

50. 50 Experimental Results at f s = 2MHz C in = 100nF + 10  FC o = 2x47nF + 4x2.2  F C 1 = 2x470nF (1206) L 1 = 161nH – 58m  L 2 = 169nH – 63m  S 1,4 = IRF8915 C in = 100nF + 10  FC o = 2x47nF + 2x47  F + 2x10  F L = 90nH – 30m  Q 1,2 = 2xIRF8915 2PIB-VD Single buck

51. 51 Efficiency Comparison @ f s = 2MHz

52. 52 ConclusionsSummary The present power supply architecture at LHC will no longer be sustainable in the future upgrades Distributed power supply architectures based on DC- DC converters are proposed High step-down ratio topologies are the key for increasing power distribution with the same cabling High conversion efficiency as well as low switching noise are mandatory Future investigations Radiation tolerance components and technologies must be selected More intensive investigations on switching noise effects must be carried out