1. CI Lecture Series Summer 2010 An Overview of IQ Modulation and Demodulation Techniques for Cavity LLRF Control

2. CI Lecture Series Summer 2010 IQ Demodulator LO (Local/Reference Oscillator) IQ Modulator RF R1 C1 R2 C2 RF VIVI VQVQ Cavity LLRF Control Block Diagram

3. CI Lecture Series Summer 2010 Vector Gain and Phase Representation Where V o is the baseband scaling constant (1V as shown in the Figure). Normally V I and V Q are differential Inputs known as Baseband I and Q Voltages and represented as VBBI and VBBQ. ( Courtesy Analog Devices) Analogue Vector Modulator 90 o VQVQ VIVI RF in RF out When two 90 degrees out of phase RF signal are added, the resultant has a phase and amplitude that depends upon the amplitude levels of two signals. It is known as Vector or IQ modulation where I is the in the in-phase signal and Q is the quadrature or 90 degrees out of phase signal. Block Diagram of an IQ modulator VQVQ ө A 1 1 VIVI I Q

4. CI Lecture Series Summer 2010 Effect of quadrature phase error and amplitude offset on sidebands Vector Mod ADL5375 from Analog Devices. Typical Gain/Amplitude error of a Vector Modulator Courtesy: Hittite Microwaves IQ Gain imbalance error is due to inconsistencies between two mixers and imperfect 90 Degrees phase shift between I and Q, known as IQ phase skew error. This means that the output phase and amplitude response of a vector modulator is not completely linear. Control Angle (degrees) Gain and Phase Error of an Analogue IQ Modulator

5. CI Lecture Series Summer 2010 All Digital Vector Modulation Digital Multiplier Sine Lookup table Cosine Lookup table Digital Multiplier Q (in Digital Format) I (in Digital Format) Digital Adder DAC LO RF IF BPF Advantage is that less external components are required as all modulation can be done inside a DSP or an FPGA and a more linear response can be obtained. Disadvantage is the noise introduced by direct digital synthesis of the IF waveform. The phase noise is introduced by: 1/f Clock jitter, and as a result the timing jitter between one data step to the next on DAC input. Wander, the Low frequency jitter in FPGAs/DSPs, caused by variations in propagation delays with temperature and close in noise of the clock. DAC nonlinearities. Using a 16 bit fast DAC, ideally a phase step of about 6 milli degrees can be generated at full amplitude. Block Diagram of an All Digital Vector Modulator, implemented inside a DSP or an FPGA

6. CI Lecture Series Summer 2010 90 o VQVQ VIVI RF in LO in Analogue IQ Demodulator Noise Figure vs RF Input Level Courtesy: Device datasheet from Analog Devices Like analogue IQ Modulators, common issues with IQ Demodulators are; IQ Gain imbalance error due to inconsistencies between two mixers, is of the order of +/-0.2db in modern IQ demodulators. Imperfect 90 Degrees phase shift between I and Q. IQ DC offset error, which is residual error and I and Q outputs, and of the order of a few mV, where signal could be of the order of a few micro volts. Architecture of an IQ demodulator as shown In Device datasheet ADL5380 from Analog Devices. Note that all Inputs are differential in order to keep the noise low. Block Diagram of an IQ demodulator An IQ demodulator is a device that extracts an RF signal’s phase and amplitude information in terms of in-phase and quadrature components.

7. CI Lecture Series Summer 2010 Direct IF Sampling IQ Demodulation ADC FPGA/DSP Clock DAC VIVI VQVQ LO RF in IF I Q I and Q in digital format Block diagram of direct IF sampling IQ Demodulation. The I and Q obtained in digital format can either be used directly with an all digital IQ Modulator or can be converted to into voltages by DACs to be used with an analogue IQ modulator. Timing Diagram for Digital IQ Demodulation The IF waveform is sampled at every quarter of its time period to obtain Q, I, -Q and –I. IF and the clock must be synchronised to the same 10MHz reference. Clock Timing jitter and staggering in the FPGA/DSP propagation delay would result In errors in I and Q measurement. This error Could be significant if the FPGA has small Thermal mass and clock has a greater close in noise. Q I -Q -I ADC Clock

8. CI Lecture Series Summer 2010 Semi-Digital IQ demodulation with Digital Phase Detector and Diode Detector Digital Phase Detector ADC DSP A(t) cos θ(t) A(t) sin θ(t) Diode Detector DAC ADC VQVQ VIVI LO RF in Diode Detector (HP HSMS285): RF Power In to Voltage Out Response Courtesy: HP Device Datasheet I Q I & Q in digital format Diode detector has a linear response for input levels -25dbm to -50dbm, and is also linear for input levels -25dbm to 0dbm but with a different slope. The slope and linearity can be corrected digitally in the DSP or FPGA if all 50db dynamic range is required. Diode Detector Characteristics

9. CI Lecture Series Summer 2010 Digital Phase Detector DPD and charge pump configuration and operation (Courtesy: AN_155 Integrated Device Technology, Inc]) Output voltage of a DPD HMC439 wrt phase difference of two inputs (Courtesy: Hittite Microwaves) HMC439 works up to 1.3GHz and gives absolute phase difference between two RF inputs. The output phase difference is independent of the amplitude and is linear for all 360 degrees. It can resolve down to 8 milli degrees rms, which is mainly limited by the phase noise introduced by the digital circuitry inside the IC. This method has advantage of independent amplitude and absolute linear phase measurement, however requires external electronic circuitry to deploy DPD and the Amplitude Detector, and has an overhead of floating point sine and cosine calculations to generate I and Q.

10. CI Lecture Series Summer 2010 All different techniques of IQ modulation and demodulation mentioned above have their own advantages and disadvantages in terms of linearity, noise and ease of implementation. What method is best suited for a low level RF control, would depend upon the requirements of a particular application,