1. D.Breton, Orsay SuperB Workshop – February 16th 2009 Ongoing R&D in Orsay/Saclay on ps time measurement: a USB-powered 2-channel 3.2GS/s 12-bit digitizer D.Breton (LAL Orsay), E.Delagnes (CEA/IRFU) Séminaire DRT/LIST 08/09/08 SACLAY.

2. D.Breton, Orsay SuperB Workshop – February 16th 2009 Orsay/Saclay’s experience on SCAs: > 100k channels working worldwide HAMAC : 1992-2001 ATLAS calorimeter 12 channels / 144 pts Fe = 40 MHz BW = 10 MHz Dyn = 13,6 bits DMILL 0.8 µm MATACQ : 1999-2003 Matrix structure 1 channel, 2560 pts Fe = 50 MHz-2GHz BP = 300 MHz Dyn = 13.5 bits AMS 0.8 µm (PATENT) PIPELINE : 2001-2002 METRIX 1 channel System on chip integrating 1 MATACQ SAM 2004-2005 HESS2 2 channels / 256 pts Fe= 400 MHz-3.2GHz BW = 500 MHz Dyn > 12 bits AMS 0.35 µm FastSampler 2 channels / 1024 pts Fe = 5GHz, BW>700MHz Dyn = 12 bits AMS 0.35 µm Future Continuous Sampler 1 GS/s- 12 bits PATENT Design in 2009 FastSampler Fe = 10GHz, BW>1GHz > 5000 pts ? AMS 0.18 µm Under design

3. D.Breton, Orsay SuperB Workshop – February 16th 2009 The SAM (Swift Analog Memory) chip 2 differential channels 256 cells/channel BW > 450 MHz Sampling Freq 400MHz->3.2GHz High Readout Speed > 16 MHz Smart Read pointer (integrates a 1/Fs step TDC) Few external signals Many modes configurable by a serial link. Auto-configuration @ power on AMS 0.35 µm => low cost for medium size prod NIM A, Volume 567, Issue 1, p. 21-26, 2006 6000 ASICs manufactured, tested and delivered in Q2 2007

4. D.Breton, Orsay SuperB Workshop – February 16th 2009 Principle of the SAMPLING MATRIX Short DLL: less jitter Individual delay servo-control / column: stability 1 amplifier/line Parallelized Readout

5. D.Breton, Orsay SuperB Workshop – February 16th 2009 Advantages/ Drawbacks of the Sampling MATRIX structure Short DLL: –smallest jitter. –junction between DLL. –potential coupling between Analog Signal and DLL control voltage. 1 servo control of Delay / Col: => high stability. Analog Input Buffering: –High input impedance: Linearity. No DC input current No Ringing. Flat response –Power consumption. –BW limitation Analog Bus Split in divisions : lines –shortest analog bus : More uniform bandwidth. less analog delay along the bus. –Parallel readout => faster readout. –1 buffer / line : Better (analog BW/Power consumption) FOM. Spread of the buffer bandwidth. Offset between lines (corrected by DAC on-chip). Initial Philosophy: no off-chip correction (pedestal, amplitude, time) => limit the external computing.

6. D.Breton, Orsay SuperB Workshop – February 16th 2009 Mismatches of components in the delay chain: => spread of delay duration. => error on the sampling time. => fixed for a given tap => fixed pattern aperture jitter Spread of single delays => time DNL. Cumulative effect => time INL. Systematic effect => correction is feasible if cell index is known => good calibration is required. But effect may change with time, temperature, … Fixed Pattern Apperture Jitter

7. D.Breton, Orsay SuperB Workshop – February 16th 2009 2 sources of aperture jitter : Random aperture jitter (RAJ). Fixed Pattern Aperture Jitter (FPJ). Inside the DLL jitters are cumulative. Assuming there is no correlation: For RAJ, the aperture jitter @ tap j will be if  Rd is the random jitter added by a delay tap For FPJ for a free running system if the total delay is servo-controlled if  FPd is the random jitter added by a delay tap (  DNL) and N is the DL length. Short servo-controlled DL => Less Jitter (both kinds) Jitter vs DLL length

8. D.Breton, Orsay SuperB Workshop – February 16th 2009 Variable BW along the SCA. Analog in Analog bus is a RC delay line:  delay depends on the sampling cell position.  the overall bandwidth also, especially if it is not limited by an input amplifier or that of the intrinsic sampling cell. Short analog busses are better for BW uniformity => segmentation

9. D.Breton, Orsay SuperB Workshop – February 16th 2009 The SAM-USB board SAM Chip Dual 12-bit ADC 1 GHz BW amplifier. µ USB Reference clock. Up to 200MHz => 3.2GS/s 2 analog inputs. DC coupled Trigger comparators Ext clk & Trigger inputs Pulsers for reflectometry applications Power consumption < 2.5W

10. D.Breton, Orsay SuperB Workshop – February 16th 2009 Test results: Bode plot Input Dynamic range can go up to 4V differential  12.6 bits Dynamic range. Max Sampling Frequency > 3.2 GS/s 450 MHz - 3dB BW (for a full range signal): ~800 MHz roll off point –convolution of SAM + on_board 1GHz amplifier. –no ringing.

11. D.Breton, Orsay SuperB Workshop – February 16th 2009 Test results: crosstalk vs frequency Xtalk < 1% even for high frequencies

12. D.Breton, Orsay SuperB Workshop – February 16th 2009 Test results: short pulse sampling 1ns FWHM pulse sampled @ 3.2GS/s (75mV) single shot [mV] 300ps/cell

13. D.Breton, Orsay SuperB Workshop – February 16th 2009 Test results: Reflectometer mode single shot Original target application of the board. 2 mm precision reached (in repetitive mode).

14. D.Breton, Orsay SuperB Workshop – February 16th 2009 Timing resolution. First, without any correction 2 methods used: –measurement of ENOB on sinewaves. –measurement with pulses.

15. D.Breton, Orsay SuperB Workshop – February 16th 2009 ENOB measurement. ENOB is not Log( Max signal/noise)/ Log(2) as often said. ENOB = (10 Log (sinus power / residues power) -1.76)/6.02. Depends on input sinewave frequency, noise & jitter. contribution of jitter to ENOB = (20 Log (2.Pi. .F sine ))-1.76)/6.02. 197 MHz sinewave @ 3.2GS/s  meas consistent with 25ps rms

16. D.Breton, Orsay SuperB Workshop – February 16th 2009 Timing Measurement with pulses. asynchronous pulse with fixed amplitude summed with delayed (by cable) pulse. timing of two pulses extracted by fixed threshold crossing (determined by simple linear interpolation.  delay = 35ps rms => 25ps for each edge Consistent with ENOB measurement. Pulse timing can be improved by using more than 2 samples => To Be Done

17. D.Breton, Orsay SuperB Workshop – February 16th 2009 Extraction of fixed pattern and random jitter. Method: 197MHz sinewave sampled by SAM search of zero-crossing segment => length and position (cell). Histogram of length[position]: –propor. to time step duration (assuming sine = straight line). –small bias due to sinewave curvature (<1.7ps rms/ 197MHz sine) –mean_length[position] = fixed pattern effect –sigma_length[position] = random effect

18. D.Breton, Orsay SuperB Workshop – February 16th 2009 Fixed pattern jitter DNL => modulo 16 pattern. Time step spread = 6.6 ps rms INL => modulo 16 pattern + slow pattern. “Absolute time” spread = 23 ps rms (100 ps peak-peak) Seems to be the major part of the jitter. Position correlated => could be corrected (off-chip) => TO BE DONE Advantage of servo-controlled structure: very small dependance to time and temperature

19. D.Breton, Orsay SuperB Workshop – February 16th 2009 Random jitter With random trigger : jitter floor ~ 2.5 ps rms but with larger jitter on “transition” samples (16 ps). Mean jitter ~ 5 ps Understood: due to the clock jitter which can be seen only on the last cell of the DLLs Source is unknown yet: could be the board (FPGA) or the chip Next board will have a direct connection between oscillator and SAM to farther study this problem.

20. D.Breton, Orsay SuperB Workshop – February 16th 2009 Recording of a MCPPMT pulse in Jerry’s lab Unfortunately, the board was equipped with a 100 MHz oscillator => the wave was sampled at only 1.6 GHz! ~ -1V 1.25 ns / div

21. D.Breton, Orsay SuperB Workshop – February 16th 2009 R&D on a ps TDC in IBM 130nm technology We are collaborating to the design of a new TDC in the IBM 130nm technology This is a collaboration between Orsay, Saclay, and the University of Chicago (with the help of Gary Varner). The goal is to reach the ps precision thanks to the addition to an usual DLL based TDC of analog memories sampling at very high frequency (10 to 40GS/s). Input clock frequency should be 312.5 MHz We started designing the first prototype  main characteristics are almost fixed now  It should include a complete measurement channel In the near future, we aim at building a 16-channel chip with integrated output buffers. These chips will be used at the output of fast PMT’s –We already have a SiPM test bench here at LAL driven by the “instrumentation” group –This bench will soon be extended to MCPPMT’s An ANR file has been filed in November for this R&D. It covers both the electronics, detectors and photo-detectors aspects.

22. D.Breton, Orsay SuperB Workshop – February 16th 2009 Conclusion We built a USB board to push the SAM chip towards its limits. Timing measurements showed a timing resolution of ~25 ps rms without any off- chip correction. Timing resolution with correction and using several samples is under study. Very small random jitter (few ps), mainly due to clock jitter. => work was done to optimize the board performances. Tests have given us new guidelines for future chips to improve timing performances. We are now convinced that a single chip can’t be optimum for all applications (long depth vs time precision). Next circuit will be submitted soon: 5GS/s sampling freq, larger BW (700MHz ?), same techno (0.35µm), larger depth (1024 pts/ch) => target = precision time measurement Upgraded version of the SAM-USB board will be available within the next days. Can be used for low cost fast detector testing (already compatible with next circuit). Will be tested with MCPPMT’s. A new ps TDC is under design.