1. PLL Sub System4 PLL Loop Filter parameters: Loop Type and Order
Passive/Active Loop topologies
Loop Filter Design and Matlab loop Analysis
More: Impact of open loop parameters variations
Impact on open loop parasitic Poles and Zeros variations
PLL noise (and Jitter..) performance
CDR (Clock Data Recovery)
Loop filter ‘Calculator’:

2. Definition: Closed and Open loop TF

3. Definition: Loop Type and Order
Type of the loop defined as its integrators number at its open loop tf,
Typical PLL will be type I or II, (VCO contribute one integrator)
the main advantage of type I is faster settling times. The advantage of
type II is that it allows the loop filter output to achieve arbitrary
DC value while forcing the phase error (input of loop filter..) to
have a steady state value of zero. The DC level shifting property of
an integrator in contrast to gain stage is illustrated at the following figure.
This alows well consistent phase error but also easier matching with the
vco controlled volatge (Vc) for optimal vco frequency span.

4. Definition: Loop Type
Type I doesn't ‘span’ the full VCO range, typically Kvco is high for wide
puling range and PLLBW is small for noise reduction BOTH dictate lower
gain on loop filter , consequently it doesn’t have enough gain to ‘support’
VCO required span, the DAC helps.

5. Definition: Loop Type
Type II disadvantage is that it yields undesired peaking behavior
In the closed loop TF, also it increases the CL settling time of the PLL.
The key parameter which dictated these is the ratio of open loop zero Fz
to the closed loop BW, Fo. note that Fz is included at the open loop tf to
achieve stability. As indicated here as Fz/Fo increased (typically is 1/6 to
1/10) the peaking Magnitude and settling time increase too.

6. Definition: Loop order
Order is denoted as n, and defined according to the rolloff characteristic
Of the closed loop magnitude response (G(f))

7. Passive/Active realization of PLL Type/Order
Advantage of passive implementation: power and noise

8. Loop Filter Design and Matlab loop Analysis
We saw..PLL is 2nd-order system similar to mass-spring- or RLC
PLL may be stable or unstable depending on phase margin (or damping factor).
Phase margin is determined from linear model of PLL in frequency-domain.
Stability affects phase error, settling, jitter.
PLL acts as a low-pass filter with respect to the reference.
Low-frequency reference modulation (e.g.spread-spectrum clocking) is passed to the VCO clock.
High-frequency reference jitter is rejected.
“Bandwidth” is the frequency at which the PLL begins to lose lock with the reference (-3dB) (‘Natural Frequency’) .
PLL acts as a high-pass filter in respect to VCO noise.
Bandwidth affects phase error, settling, jitter.
THUS: Find phase margin/damping using MATLAB, loop equations, or simulations

9. Loop Filter Design and Matlab loop Analysis
Bode Plot
Used to analyze frequency domain behavior
Y-axis: gain in dB. E.g. 20dB=10X gain. 3dB=1.4X
X-axis: frequency. Log scale
Assuming “left-hand-plane” location:
Pole: -20db/dec magnitude loss and -90° phase shift. Capacitor  pole.
Zero: +20db/dec magnitude and +90° phase shift. Resistor  zero.

10. Loop Filter Design and Matlab: Phase tracking vs. Peaking
Peaking at low and high damping factors  bad
Damping ~ 1  good compromise
Phase Tracking  think “accumulated” jitter or phase error
VCO frequency peaking (i;e; period jitter) similar to phase peaking

11. Loop Filter Design and Matlab: Phase tracking vs. Peaking
Less ringing and overshoot as   1

12. Loop Filter Design and Matlab: Phase tracking vs. Peaking
Severe overdamping  ringing and overshoot

13. Matlab: VCO Jitter (df/f) vs. Damping
Low damping  less period jitter, slower response, more phase error

14. Matlab: VCO Jitter (df/f) vs. Damping
High damping  low oversampling (large R) causes oscillation

15. Other PLL applications: CDR, FM demodulator..
The Phase detector is mixer, thus demodulate the modulation signal
from the carrier (if Wc = local VCO frequency at receiver )

16. More on PLL applications..
Impact of open loop parameters variations
Impact on open loop parasitic Poles and Zeros variations
PLL noise (and Jitter..) performance
CDR and FM demodulators architectures