1. Reconfigurable Computing - Performance Issues John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound, Western Australia

2. FPGA Architectures  Design Flow  Good engineering practice requires that design exercises should follow a defined procedure  User’s specification  This is your starting point  It may take several forms 1.Informal requirements given to you by your user / client / … 2.Formal written requirements All functional and non-functional requirements are precisely stated Sometimes resulting in a very large (and dull) document! 3.Something in between Your tutorial assignment was in this category Mostly formal, but with some gaps you would need to fill in Using research / further discussion with client / … etc

3. Typical FPGA Architecture  Logic blocks embedded in a ‘sea’ of connection resources  CLB = logic block IOB = I/O buffer PSM = programmable switch matrix  Interconnections critical  Transmission gates on paths  Flexibility  Connect any LB to any other  but  Much slower than connections within a logic block  Much slower than long lines on an ASIC Aside: This is a ‘universal’ problem - not restricted to FPGAs! Applies to custom VLSI, ASICs, systems, parallel processors Small transistors  high speed  high density  long, wide datapaths

4. Logic Blocks  Combination of  And-or array or Look-Up-Table (LUT)  Flip-flops  Multiplexors  General aim  Arbitrary boolean function of several variables  Storage  Adders are critical  All modern FPGAs have ‘fast carry logic’  High speed lines connecting LBs directly  Very fast ripple carry adders

5. Ripple Carry Adder  The simplest and most well known adder  Time to complete  n x propagation delay( FA: (a or b)  carry )  We can do better than this - using one of many known better structures  but  What are the advantages of a ripple carry adder?  Small  Regular  Fits easily into a 2-D layout! FA a1a1 b1b1 c in c out s1s1 FA a0a0 b0b0 c in c out s0s0 FA a n-1 b n-1 c in c out s n-1 FA a n-2 b n-2 c in c out s n-2 carry out Very important in packing circuitry into fixed 2-D layout of an FPGA!

6. Ripple Carry Adders  Ripple carry adder performance is limited by propagation of carries FA a1a1 b1b1 c in c out s1s1 FA a0a0 b0b0 c in c out s0s0 FA a n-1 b n-1 c in c out s n-1 FA a n-2 b n-2 c in c out s n-2 carry out FA a3a3 b3b3 c in c out s3s3 FA a2a2 b2b2 c in c out s2s2 LB A 2-bit adder fits in a Xilinx CLB (enough logic for 5 inputs and 2 outputs) But these signals would need to be carried by the general routing resources (slow!) (In fact, you can’t fit a 2-bit adder with carry out in a CLB because there aren’t enough outputs! The fast carry logic provides special (low R) lines for carry-in and carry-out  fast adder with 2 bits/CLB

7. ‘Fast Carry’ Logic  Critical delay  Transmission of carry out from one logic block to the next  Solution (most modern FPGAs)  ‘Fast carry’ logic  Special paths between logic blocks used specifically for carry out  Very fast ripple carry adders!  More sophisticated adders?  Carry select  Uses ripple carry blocks - so can use fast carry logic  Should be faster for wide datapaths?  Carry lookahead  Uses large amounts of logic and multiple logic blocks  Hard to make it faster for small adders!

8. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry Here we build an 8-bit adder from 4-bit blocks ‘Standard’ n -bit ripple carry adders n = any suitable value

9. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry After 4*t pd it will produce a carry out This block adds the 4 low order bits These two blocks ‘speculate’ on the value of cout 3 One assumes it will be 0 the other assumes 1

10. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry After 4*t pd it will produce a carry out This block adds the 4 low order bits After 4* tpd we will have: sum 0-3 (final sum bits) cout 3 (from low order block) sum0 4-7 cout0 7 (from block assuming 0 c in ) sum1 4-7 cout1 7 (from block assuming 1 c in )

11. Carry Select Adder n-bit Ripple Carry Adder a 0-3 sum 0-3 b 0-3 cin a 4-7 sum0 4-7 b 4-7 cout 7 cout 3 0 sum1 4-7 cout 7 1 n-bit Ripple Carry Adder b 4-7 n-bit Ripple Carry Adder 01 sum 4-7 01 carry Cout 3 selects correct sum 4-7 and carry out All 8 bits + carry are available after 4*t pd (FA) + t pd (multiplexor)

12. Carry Select Adder  This scheme can be generalized to any number of bits  Select a suitable block size ( eg 4, 8)  Replicate all blocks except the first  One with c in = 0  One with c in = 1  Use final c out from preceding block to select correct set of outputs for current block