2. Beam Secondary Shower Acquisition System: ICECAL_V3 Mezzanine Board, initial developments BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 2 Jose Luis Sirvent Blasco PhD. Student STUDENT MEETING 01/12/2014

3. 1. Introduction 1.1 Starting point: Developments for ICECAL_V2 board stopped: Only one channel No Multiplexer Need to sample with 2 ADC No CLK tuning possibilities Developments for ICECAL_V3 board started: E.Picatoste kindly provided schematic of his evaluation board. Thanks to him I do not start from scratch! ICECAL_V3 is much closer to the production prototype 4 Channels + Multiplexer + Driver + Delay Line for CLK tunning BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 3

4. 1. Introduction 1.2 The original ICECAL_V3 Board BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 4

5. 1. Introduction 1.3 Needed Modifications: Dual Channel 12 bits ADC: AD9238 Digital Output: 2x12 CMOS @ 40Mbps  Needed LVDS @ 80Mbps Vcc: 3.3v  That it’s ideal for us Radiation hard: To be characterized  Needed RH > 1KGy Input diff Swing : 2Vpp  Suits perfectly ICECAL Input Vcm: 1.5v  Suits perfectly ICECAL Power Stage: Needed to include 2.5v @ 3.3V for Igloo2UMd Mezzanine Connectivity: Needed to include SAMTEC QSH-120-01-L-D-A Connector In general: Adapt for our needs (remove unnecessary components) Add new components for GBTx compatibility (as I did with QIE10 boards) BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 5

6. 2. Looking for an alternative ADC 2.1 Desired Specifications BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 6 CharacteristicValue Resolution12 – 14 bits Channels 2 – 4 Sampling Freq. > 40MSPS Digital OutputsLVDS DDR @ 80Mb/s LVDS DDR @ 160Mb/s LVDS DDR @ 320Mb/s Analog InputDiff. Swing: 2Vpp Vcm : 1.5V ADC ConfigurationParallel Power supply3.3V Radiation TID > 1KGy (Characterized)

7. 2. Looking for an alternative ADC 2.1 The survey BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 7

8. 2. Looking for an alternative ADC 2.1 The survey BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 8 The Rad-charactericed ones compatibles with GBTx are not compatibles with ICECAL ADC Driver needed to adapt levels

9. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 9 2. Looking for an alternative ADC 2.2 ADC Drivers for Level shifting (ICECAL  ADC) Carefully studying the datasheet is sometimes not enough: Components characterized @ +-5V or +5V (We need 3.3v) Input Diff. Swing and Input Vcm needs to be verified Need to know reachable output levels Two models selected for evaluation: THS4521 (Texas Instruments) AD8138 (Analog Devices)

10. 3. Testing Set-up Development of an small board for testing both ampliffiers: They share the same pinout (The same board can be re-used) Very simple Differential to Differential Amplif G = 1v/v Vcm at output controlled by Vocm Pin BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 10

11. 3. Testing Set-Up 3.1 First measurement Round (Same config) AD8138 BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 11 Overshoot found (Spected) Good Timing characteristics With Vcc 0 - 3.3v Vcmo cannot be < 1.3V THS5421 (Res. Values not optimal) Overshoot found (Spected) Good Timing characteristics No problems reaching Vocm < 0.9V

12. 3. Testing Set-Up 3.2 Second measurement Round (THS4521) BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 12 Optimizing resistor values (All R = 1K) Source well loaded (no Cfs) Faster rise-time but bigger overshoot Set-up time ~ 15ns (Careful! Our period is 25ns) Input Period 100ns Input Period 40ns (As ICECAL)

13. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 13 3. Testing Set-Up 3.2 Second measurement Round (THS4521) Controlling the Overshoot and Rising time with Cf Suitable value Cf = 4.7 pF Overshoot reduced to ~ 3% Rise time increased ~ 7ns Quite nice but still not perfect… will a nice board improve something??

14. 4. Second Testing Set-up 4.1 Same but in a nicer way SMD resistors and caps Ground plane very near components Shorter connections Grounded Board BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 14

15. Same configurations Some resistor values may vary a bit BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 15 4. Second Testing Set-up 4.2 Comparing boards performance with THS4521 The ugly boardThe nice board The main difference relies on the flatness of the plateau (less ringing for overshoot) Signal Period  100ns

16. Same configurations Some resistor values may vary a bit BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 16 4. Second Testing Set-up 4.2 Comparing boards performance with THS4521 The ugly boardThe nice board The main difference relies on the flatness of the plateau (less ringing for overshoot) Signal Period  40ns

17. 5. Some conclusions Selected ADC:ADS4245 ADC Driver candidate: THS4521 Maybe I can find faster amplifiers, this one is 145Mhz I’ll invest a bit more of time on this just in case better components could be found. Analog signal quality it’s an important factor on this design! BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 17