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Feedback Systems Update Alessandro Drago SuperB General Meeting Perugia 16-19 June 2009.

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Presentation on theme: "Feedback Systems Update Alessandro Drago SuperB General Meeting Perugia 16-19 June 2009."— Presentation transcript:

1

2 Feedback Systems Update Alessandro Drago SuperB General Meeting Perugia 16-19 June 2009

3 2 Why a new design The fast advances of the electronics components make obsolete the present feedback systems Low emittance beams ask for low impact feedback systems How Previous software/hardware legacy Only one digital processing unit design for both longitudinal & transverse Low noise front end receiver 2 nsec longitudinal & transverse kickers Reuse of old systems when possible In particular, reuse of the power amplifiers (~50k$ for each 250W unit)

4 3 Gproto / iGp evolution After a unique first phase collaboration design, four slightly different hardware layouts have been designed [KEK, SLAC, DIMTEL + old Gproto] Dmitry Teylman (DIMTEL Inc.) is going to start an iGp new release with 12 bits ADC: he claims that it will be ready for the begin of next year The new iGP will have the same price list [100k$ + tax - %discount] Interesting connected option: low noise front end [ 30k$ + tax - %discount] DIMTEL does NOT sell the FPGA source code!

5 4 Focusing on the digital processing unit: to do list for in-house R&D starting from Gproto / iGP experience 1)Analog to digital conversion @ 12 bits 2)Digital to analog conversion @ 16 bits 3)DSP in FPGA to implement FIR filters: gateware and firmware 4)Software: Operator Interface with connections to the systems 5)Final PCB including ADC, DAC, FPGA and interfaces

6 5 ADC

7 6

8 7 The dynamic range in DAFNE feedback analog blocks is in the range 78 dB – 88 dB

9 8 ADC evaluation board ADS5463EVM NameADS5463 Evaluation ModuleStatusACTIVE Price (US$) $299.00

10 9 DAC MAX5891 16-Bit, 600Msps, High- Dynamic- Performance DAC with LVDS Inputs

11 10 DAC evaluation board Price: $ 145,00

12 11 DAC evaluation board

13 12 Xilinx FPGA: Virtex-II  Virtex-5  Virtex-6

14 13 Virtex-5 Evaluation Boards [up to now no Virtex-6 boards] Virtex-5 LXT/SXT FF1738 Prototyping –AFX-FF1738-500 PLATFORM –Platform with Xilinx FPGA $3100 Virtex-5 LXT/SXT FF665 Prototyping –AFX-FF665-500 PLATFORM –Platform with Xilinx FPGA $2000 XtremeDSP Development Platform — Virtex-5 FPGA ML506 Edition with XC5V-SX50T-FFG1136 (288 DSP inside) $1195

15 14 FPGA Evaluation Boards AFX-FF1738-500 AFX-FF665-500 ML506

16 15 Gproto (Virtex-II) block diagram External PC

17 16 Using ML506 it is possible to include the pc inside the FPGA

18 17 800euro 1100$ 300$ 1500euro

19 18 This similar project is financed by CSNV Human interface by a browser

20 19 Another Virtex-4 solution Agilent U1083A- 003 Acqiris RVM4400 High-Speed 6U VME/VXS ADC/DAC Module 10-bit ADC, 14- bit DAC, 1.2 GS/s Price ~24 k euro

21 20 Conclusion A new version of iGP @ 12/16 bits should be ready at the begin of next year by DIMTEL, Inc. [but no FPGA source code] The in-house upgrade of feedback digital processing unit is underway Different design solutions are available, but it is necessary to know the amount of bunch-by-bunch feedback budget, when it will start and who will pay (SuperB TDR, NTA, CSNV, others...)


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