1. 1 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato LePIX – monolithic detectors in advanced CMOS Collection electrode High energy particle Electronics Sensitive layer Develop monolithic pixel detectors integrating readout and detecting elements by porting standard 90 nm CMOS to wafers with moderate resistivity. Reverse bias of up to 100 V to collect signal charge by drift. Scope Develop and optimize the sensor. Low power (~1µW/pixel) front end electronics by low detector capacitance. Assessment of radiation tolerance. Assessment of crosstalk between circuit and detecting elements. Key priorities

2. 2 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato LePIX – goals and motivations Good radiation hardness (charge collection by drift). Feedback from foundry there are strong perspectives to obtain more than 10 µm depletion. Parallel signal processing for every pixel, time tagging at the 25 ns level. Monolithic integration -> low capacitance for low power consumption = KEY TO LOW MASS. Target is 10-20 mW/cm2 in continuous operation. High production rate (20 m2 per day…) and cost per unit area less than traditional detectors. Low K dielectrics in the metal stack beyond 130 nm. Deep submicron CMOS Non-standard processing on very high resistivity substrate or MAPS based with serial readout not necessarily always compatible with future colliders: collection by diffusion very much affected by radiation damage (and low signal anyway). Note on «traditional» detectors

3. 3 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato Submission - Overview Non-standard: ESD protection, special layers, mask generation, guard rings. 7 different chips submitted: 4 test matrices, 2 types of readout and 2 collection electrode sizes. 1 diode for radiation tolerance. 1 breakdown test structure. 1 transistor test: already submitted once in test submission. Actually two submissions made: very same design but different substrates: standard and high resistivity one. Submission peculiarities MatrixesDiodeBreakdown test Transistor test

4. 4 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato Measurements – overview Synchronize biasing and measurements to optimize chip survivability. Completely automated chip feeding and readout allows for quick measurements of pixel matrixes. Padova Setup

5. 5 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato Measurements – the pulse! Matrixes Pix 1 sgn Pix 1 refPix 2 sgnPix 2 refPix 3 ref 70 mV

6. 6 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato Conclusions  LePIX tries to exploit very deep submicron CMOS on moderate resistivity:  Radiation hardness (charge collection by drift).  Low power consumption: target 20 mW/cm2 in continuous operation.  Monolithic integration -> low capacitance for low power & low mass (needs work on digital part to fully take advantage of the gain in the analog)  High production rate (20 m2 per day…) and cost per unit area less than traditional detectors  Low C is key to reach low power, pulse measurement illustrates very low capacitance.  Breakdown voltage > 30V on standard silicon promising.  First submission has shown the exercise is not easy, now implementing the corrections.

7. 7 /28 LePIX – Front End Electronic conference – Bergamo 25 May 2011 – Piero Giubilato LePIX – collaboration Collaboration between CERN & INFN (Torino, Bari, Bologna, Padova) Jeff Wyss (70%), Marta Bagatin (30%), Andrea Candelori (30%), Luca Silvestrin (70%) + Devis Pantano (50%) Missioni Interne 2 keuro Missioni Estero 3.5 Consumo 15.5 5 m/uomo LOE 2 m/u OM