1. EKT 221 / 4 DIGITAL ELECTRONICS II SUBJECT INTRODUCTION

2. Lecturer: 1) Pn Aznor Hanah Abdul Halim Room 3 KKF 8,Taman Kuala Perlis. Tel: 04-9854058 / 012-5053235 Email: aznor@unimap.edu.myaznor@unimap.edu.my 2) En Mohd Sani Room 3 KKF 6,Taman Kuala Perlis. Email: sani@unimap.edu.mysani@unimap.edu.my 3) En Phak Len Email: phaklen@unimap.edu.my

3. PLV: 1) Pn Hazila Othman Email: hazila@unimap.edu.my 2) En Mohd Azizi Email: sani@unimap.edu.mysani@unimap.edu.my

4. Grading: 50% - Final exam 50% - Course Work - Mini Project = 10% 50% - Lab = 20% (Lab + Lab Test) - Tests = 15% - Tutorial/Assignment/Quizzes = 5%

5. Main Text Book: Digital Electronics Design, Prentice Hall. Price = RM 58. Used in Digital I & Digital II.

6. Other References: Floyd, Digital Fundamentals, Prentice Hall. M. Morris Mano & Charles R. Kime, Logic and Computer Design Fundamentals, 3 rd Edition, Prentice Hall. Mano & Ciletti, Digital Design, 4 th Ed.

7. Teaching Plan

8. Important Dates ● Week 7 (23 – 29 Aug 2010) – Test 1 – Lab Test ● Week 13 ( 18 – 24 Oct 2010) – Test 2

9. Mini Project ● Groups of 4 (max). ● Title can be your own, recommended to work towards the RPS i-project. – Please consult lecturers or plvs for clarification on project suitability. Will be asked to submit proposal.

10. Chapter 1 : Registers & Register Transfers  Registers, Microoperations & Implementations  Counters, register cells, buses & serial operations  Counters  Register cell design  Multiplexer and bus-based transfers for multiple registers  Serial transfers & microoperations OUTLINE

11. Chapter 2 : Sequencing & Control  State machine  Datapath & control  Algorithmic State Machine (ASM)  Hardwired control  Microprogrammed control OUTLINE

12. Chapter 3 : Memory Basics  Memory definitions  Random Access Memory (RAM)  Static RAM integrated circuits  Arrays of SRAM IC  Dynamic RAM IC  DRAM types  Arrays of DRAM IC OUTLINE

13. Chapter 4 : Computer Design Basics  Datapath ALU  Barrel Shifter  Control Word OUTLINE

14. LABS & TUTORIALS ● Monday -Group 20 ● Thursday – 8am -Group 4 – 11am - Group 3

15. Course Outcomes (COs) ● CO1: Ability to design digital systems at the sub- system level ● CO2: Ability to use appropriate design software tool to program the target hardware ● CO3: Ability to test and verify the digital design on the hardware platform ● CO4: Ability to participate effectively in a team

16. What to expect & do … In Class ● To do: – Sign up the attendance sheet – Do not be NOisY.. – Pay attention ● To expect: – Surprise quizzes – In-class assignments

17. What to do after class … ● Read the textbook ● Answer Tutorial Questions

18. What to do BEfore lab … ● Download the lab sheet and relevant materials from portal.

19. Altera Max+Plus II Altera UP-2 Training Board

20. soMe miNi pRoJect eXaMples

21. Mini Project Examples Source: Floyd’s

22. Tablet Counting and Bottling Control System Chapter 1

23. Figure 1–58 Simplified basic block diagram for a tablet-counting and bottling control system. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

24. Fluid Storage Tank Controller Chapter 5

25. Figure 5–48 Fluid storage tank with level and temperature sensors and controls. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

26. Voting System Chapter 6

27. Figure 6–14 A voting system using full-adders and parallel binary adders. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

28. Traffic Lights Controller Chapter 6, 7, 8

29. Figure 8–63 Traffic light control system block diagram. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

30. Figure 8–64 Sequence of traffic light states. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

31. Figure 8–66 State diagram for the traffic light control system. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

32. Figure 8–70 Block diagram of the complete traffic light control system. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

33. Traffic Lights Controller Appendix B

34. Figure B–1 Interface circuit used with model traffic lights. One circuit drives one light. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

35. Figure B–1 (continued) Interface circuit used with model traffic lights. One circuit drives one light. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

36. Figure B–2 Interface circuit used with actual traffic lights. One circuit drives one light. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

37. Figure B–2 (continued) Interface circuit used with actual traffic lights. One circuit drives one light. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

38. Security Code Controller Chapter 9, 10

39. Figure 9–44 Basic block diagram of the security system. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.