1. Vladimir Gromov, NIKHEF, Amsterdam. GOSSIPO-3 Meeting March 17, 2009. Specification of the On-pixel LDO for powering of the local oscillators

2. GOSSIPO-3 Meeting 17/03/2009 V. Gromov 2 Low-Drop Regulator Vdd_in Vdd_out = Vref ● (1+R1/R2) Voltage Reference Circuit Id !!! Stable output voltage → low output-to-input sensitivity so that: ∆Vdd_in ● [d(Vdd_out)/d(Vdd_in)] < 20mV !!! Power Supply Current: Id = 100μA ● Averaged_Number_of_active_osc. !!! Instability of the value of Vdd_out due to fluctuation of the number of simultaneously active pixel should be less than 20mV External capacitor ??? ∆ VDD < 50 mV Accumulated error < 6% (1.8 ns or 1 TDC) 25ns over the statistics of pixel occupancy R1 R2 Vref Vdd_in

3. GOSSIPO-3 Meeting 17/03/2009 V. Gromov 3 Functionality of the Reference circuit - Low sensitivity to the variation of the “dirty” power supply voltage (Vdd_in). Could be solved by using passive low-pass RC-filters (see later). - Vref needs to be tunable in order to compensate for the process-related spread of frequency of the local oscillators → variation in corners: ± 25% - Resolution does not need to be better than the channel-to-channel mismatch: → channel-to-channel variation : ± 1.5% 50/3 = 17 → 4bit DAC -Vref must be able to compensate for the temperature related shift of the frequency of the local oscillator → + 2% / 10 ◦ C d(Vref)/dT = - 2% / 10 ◦ C Voltage Reference Circuit Vref Vdd_in

4. Current bandgap reference GOSSIPO-3 Meeting 17/03/2009 V. Gromov 4 Vdd Ib1 Ib2 Iref Ub1 Ub2 Ub3 Ub1 R2 R1 I2 I1 T1 T2 Iref 2 Iref 4 Iref 8 Iref = I1+I2 Iref D C R Q _Q D C R Q D C R Q D C R Q Vref Data Clock Reset Serial Link (Slow Control)

5. Performance of the present Bandgap circuit GOSSIPO-3 Meeting 17/03/2009 V. Gromov 5 Passive low-pass RC-filter Bandgap reference circuit Power Supply Ripple Rejection (PSRR) of the Bandgap reference circuit itself Power Supply Ripple Rejection (PSRR) at the output of the RC-filter

6. Input conditions: Sensitive area: 1.4cm x 1.4cm (1.96cm 2 ) Pixel size: 55μm x 55μm Number of pixels: 256 x 256 (65 536) Track occupancy: 12 (cm 2 ●BX) -1 Tracks per chip per BX (Ntr) : 24 Fluctuation of the number of the tracks per chip per BX: σ tr = √N tr = √24 ≈ 5 Average primaries per track: 10 Active pixels (number of primaries) per BX (Nact): 240 Current per active pixel (Iosc): 100μA Specification of the LDO: Average load current: Iav = 24mA = Nact● Iosc = 240 ● 100μA Peak load current (worst case): Ipeak = 44mA= Iosc ●10 ●(N tr +4●σ tr )= 100μA ● 440 Output impedance: Zout = 1 Ω= ∆20mV / ∆ 20mA tolerable voltage drop load current jump (worst case) LDO: load requirements 55μm 256pixels · 55μm =1.4cm Readout chip N tr =24 Entries Standard deviation σ tr ≈ 5 The highest track occupancy: N tr +4●σ tr = 44 GOSSIPO-3 Meeting 21/04/2009 V. Gromov 6

7. Size of the output PFET I load Vref Vout Vdd=1.2V Input conditions : Power supply voltage: Vdd=1.2V Regulated output voltage: 0.8V…1.1V Load current: 24mA ± 20mA = 4mA…44mA Specifications: Saturation voltage: Vds sat = Vdd-Vout max =1.2V-1.1V= 100mV Saturation current (worst case): Id sat = 44mA ≈4.5 ●10 10 μm 2 /(V ●sec) = 100mV ≈ 44mA → ~ 10 5 Id sat = 0.5●μ hole ●Cox ●( W/L )● Vds sat ● Vds sat = 2fF/ μm 2 = 100mV W=48 ●10 3 μm L = 0.24μm Vd sat Id sat Simulations: Id (Vd) at Vgs= -354mV Layout of the output PFET: Number of fingers:100 Width of each finger: 480μm Total width: 48 000 μm Length of each finger: 0.24μm Area: 480 μm x 70 μm = 3.36 ● 10 6 μm 2 GOSSIPO-3 Meeting 21/04/2009 V. Gromov 7

8. Topology of the LDO Uref (0..0.7V) It Uout (0….1.1V) R2(10K) R1 (5.7K) Vdd (1.2V) T1 T2 T3T4 W=48000μm L=0.24μm g out 1 Il Cgd Cl Transfer Function: Uout = Uref ● K(p) /[1+β ● K(p)] ≈ Uref ● β -1,where feedback factor: β = R2/[R1 + R2] Open loop gain: K(p) = 2 gm T1 /g out 1 ● gm T5 /g * ●1/[(1+p ●τ1) ●(1+p●τ2)] g * = g ds 5 +1/(R1+R2) + 1/Rl ≈ g ds 5 Pole #1: τ1≈ [1/ g out 1 ] ● [Cgd ● gm T5 /g * ] Pole #2: τ2 ≈ [1/ g * ] ● [C out 5 + Cl ] g ds 5 C out 5 Rl Output Impedance of the LDO: Zout = Uout / Il = 1/g * ● 1/[1+β ● K(p)] !!!! Zout ≈ 1Ω even in wide frequency band (up to 500MHz) T5 GOSSIPO-3 Meeting 21/04/2009 V. Gromov 8

9. Output impedance & stability at Cl << Cout Output Impedance of the LDO: Zout = Uout / Il = 1/[g * +pC out 5 ]●1/[1+β ● K(p)] Il=44mA → g ds 5 = 100mS Zout freq=0 = 0.07 Ω = 10 Ω / (0.6 ● 30 ● 8) → g m T5 = 800mS Zout high freq → 1/g * ≈ 10 Ω → Cgd =17pF → Cout = 37pF It = 1mA → gm T1 ≈ 24 ● It/2= 12mS → g out 1 ≈ gm T1 / 30 Cl << Cout g * ≈ g ds 5 Simulations: Uout (Il) at ∆ Il=20mA 1.7mV= 0.07 Ω ● 20mA 100mV voltage drop within 15ns Bode plot: Feedback Loop Analysis: f1= 1/ [2 ● τ1] = g out 1 / [2 ● Cgd ● gm T5 /g * ] = 0.4MHz (dominant pole) f2= 1/ [2 ● τ2] = g out * / [2 ● Cout 5 ] = 500MHz phase margin = 90° GOSSIPO-3 Meeting 21/04/2009 V. Gromov 9 Unity gain freq =4MHz 0dB line → Loop gain=1

10. Output impedance & stability at Cl >> Cout Output Impedance of the LDO: Zout = Uout / Il = 1/[g * +p(C out 5 + Cl)]●1/[1+β ● K(p)] Il=44mA → g ds 5 = 100mS Zout freq=0 = 0.07 Ω = 10 Ω / (0.6 ● 30 ● 8) → g m T5 = 800mS Zout high freq ~ 1/(freg ● Cl) → Cgd =17pF → Cout = 37pF It = 1mA → gm T1 ≈ 24 ● It/2= 12mS → g out 1 ≈ gm T1 / 30 Cl = 10μ F >> Cout g * ≈ g ds 5 Simulations: Uout (Il) at ∆ Il=20mA !!! 2mV voltage drop Bode plot: Feedback Loop Analysis: f1= 1/ [2 ● τ1] = g out 1 / [2 ● Cgd ● gm T5 /g * ] = 0.4MHz f2= 1/ [2 ● τ2] ≈ g out * / [2 ● Cl] = 5KHz (dominant pole) GOSSIPO-3 Meeting 21/04/2009 V. Gromov 10 phase margin = 90° !!! Unity gain freq =100kHz !!! Negligible fluctuations of the output voltage !!! Slow feedback loop reaction 0dB line → Loop gain=1

11. GOSSIPO-3 Meeting 06/05/2009 V. Gromov 11 Power Supply Ripple Rejection Uout / Vdd = gm ● Z * / [1+β ● K(p) ● gm ● Z * ],where Il=44mA → g ds 5 = 100mS Z * = 1/[g * +p(C out 5 + Cl)] → g m T5 = 800mS → Cgd =17pF Uout / Vdd freq=0 = 0.06 (-25dB) = 1 / [β ● gm T1 /g out 1 ]= 1/[0.6●30] → Cout = 37pF Uout / Vdd high freq ~ 1/freg It = 1mA → gm T1 ≈ 24 ● It/2= 12mS → g out 1 ≈ gm T1 / 30 g * ≈ g ds 5 Simulations: Uout / Vdd vs frequency -25dB (low frequency) Cload << Cout Cload (10μF) >> Cout !!! Large external capacitance (10μF) improves PSRR

12. Reference voltage ripple rejection Uout = Uref ● K(p) /[1+β ● K(p)] ≈ Uref ● β -1 Il=44mA → g ds 5 = 100mS → g m T5 = 800mS → Cgd =17pF Uout / Uref freq=0 = β 1 = 1+[R1/R2] → Cout = 37pF Uout / Uref high freq ~ 1/freg It = 1mA → gm T1 ≈ 24 ● It/2= 12mS → g out 1 ≈ gm T1 / 30 g * ≈ g ds 5 Simulations: Uout /Uref vs frequency Cload << Cout Cload (10μF) >> Cout f cut-off = 350 kHz f cut-off = 45 MHz !!! Large external capacitance (10μF) improves Uref RR at high frequencies. GOSSIPO-3 Meeting 06/05/2009 V. Gromov 12

13. Size of the external 10μF capacitor 1mm 0.5mm Technical/Catalog Information TACK106M002QTA VendorAVX Corporation (VA) CategoryCapacitors Capacitance 10µF Voltage - Rated 2V Tolerance±20% Package / Case 0402 (1005 metric) PackagingCut Tape (CT) FeaturesGeneral Purpose Maximum Temperature-55°C ~ 125°C Lead Spacing- ESR (Equivalent Series Resistance) 15.00 Ohm Lifetime @ Temp.1000 Hrs @ 85°C Mounting TypeSurface Mount Lead Free StatusLead Free RoHS StatusRoHS Compliant Other Names TACK106M002QTA TACK106M002QTA 478 3254 1 ND 47832541ND 478-3254-1 GOSSIPO-3 Meeting 14/05/2009 V. Gromov 13

14. Schematic of the real LDO (Cl=10μF). Vdd=1.2V Itail =100μA Vds -Vds sat = 40mV (Iload=0mA) Vds -Vds sat = 14mV (Iload=44mA ) Vds -Vds sat = 74mV (Iload=0mA) Vds -Vds sat = 283mV (Iload=44mA ) Stability: Phase Margin = 89° (Iload = 0mA) Phase Margin = 58° (Iload = 44mA) Feedback Loop Unity Gain Frequency: = 1.6kHz (Iload = 0mA) = 91kHz (Iload = 44mA) GOSSIPO-3 Meeting 14/05/2009 V. Gromov 14

15. Performance of the real LDO (Cl=10μF). Control characteristic: Uout vs Uref Uout Uref Iload = 0mA Iload = 44 mA 80mV…750mV 100mV…1.2V GOSSIPO-3 Meeting 14/05/2009 V. Gromov 15

16. Performance of the real LDO (Cl=10μF). Control characteristic: Uout (Uref) vs TEMP Iload= 0 mA Uref Uout TEMP = 0°C, 25°C, 50°C ∆ Uout = 3.6mV ∆ TEMP = 50°C Itail = 50μA, 100μA, 150μA Uref Uout Control characteristic: Uout (Uref) vs Itail ∆ Uout = 4.2mV Itail= 100μA ± 50μA GOSSIPO-3 Meeting 14/05/2009 V. Gromov 16

17. Performance of the real LDO (Cl=10μF). Control characteristic: Uout (Uref) vs TEMP Iload= 44 mA Uref Uout TEMP = 0°C, 25°C, 50°C ∆ Uout < 1 mV ∆ TEMP = 50°C Itail = 50μA, 100μA, 150μA Uref Uout Control characteristic: Uout (Uref) vs Itail ∆ Uout = 4.2mV Itail= 100μA ± 50μA GOSSIPO-3 Meeting 14/05/2009 V. Gromov 17

18. Power Supply Ripple Rejection: Uout / Vdd vs frequency Iload = 0 mA Iload = 44mA -38 dB - 59dB Reference Voltage Ripple Rejection: Uout / Vref vs frequency Iload = 44mA Iload = 0 mA f cut-off = 1.5 kHz f cut-off = 100 kHz !!! Output voltage drop is 18mV (tolerable < 20mV) in the worst case (∆ Iload=44mA) !!! PSRR is -38dB in the worst case. A ripple of 200mV will be suppressed down to 2mV !!! RVRR characteristic demonstrates the cut-off at frequencies from 1.5kHz … 100kHz. !!! Check overall Badgap ref. + RVRR. May be an additional low-pass filter (see slide 5) is not needed. Performance of the real LDO (Cl=10μF). Output impedance: Uout / Iload ∆ Uout=18mV ∆ Iload=44mA ∆ Uout=18mV ∆ Iload=44mA GOSSIPO-3 Meeting 14/05/2009 V. Gromov 18

19. Performance of the real LDO (Cl=10μF). GOSSIPO-3 Meeting 14/05/2009 V. Gromov 19 Control characteristic: Uout (Uref) in the process corners Iload = 44mA Iload = 0mA

20. Schematic of the real LDO (Ll=1uH, Rs=1Ω / 2Ω, Cl=10μF) Stability: Phase Margin = 93° (Iload = 0mA) Phase Margin = 58° (Iload = 44mA) Simulations: Uout (Il) at ∆ Il=20mA 40mV voltage drop (Rs=2Ω) 20mV voltage drop (Rs=1Ω) !!! Output voltage drop is proportional to the value of serial resistor (Rs) !!! ∆U < 20mV → Rs < 1Ω (ERS = Equivalent resistance of the capacitor) vendors: dig-key, EPCOS, MURATA, PANASONIC, TAIYO YUDEN GOSSIPO-3 Meeting 25/05/2009 V. Gromov 19