1. COE 360 Principles of VLSI Design Delay

2. 2 Definitions

3. 3

4. Propagation delay the propagation delay, or gate delay, is the length of time which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change.

5. Contamination Delay The contamination delay (denoted as tcd) is the minimum amount of time from when an input changes until any output starts to change its value.

6. Definitions Propagation Delay – Time from last input change until last output change. (Input at steady state to output at steady state.) Contamination Delay – Time from first input change until first output change. (Input contaminated to output contaminated)

7. 7 Definitions When an input changes, the output will retain its old value for at least the contamination delay. It takes on its new value in at most the propagation delay.

8. 8 Definitions Propagation and contamination delay times are also called max-time and min-time, respectively. The gate that charges or discharges a node is called the driver and the gates and wire being driven are called the load. Propagation delay is usually the most relevant value of interest, and is often simply called delay.

9. Example c_in a0 b0 a1 b1 s0 s1 c_out mux Length 5 Length 1 ripple carry adder 1 0

10. 10 Definitions

11. Sometimes we differentiate between the delays for the output rising, t pdr / tcdr The output falling, t pdf /t cdf.

12. 12 Definitions A timing analyzer computes the arrival times, i.e., the latest time at which each node in a block of logic will switch. The nodes are classified as inputs, outputs, and internal nodes.

13. Definitions The user must specify the arrival time of inputs and the time data is required at the outputs.

14. 14 Definitions The arrival time a i at internal node i depends on the propagation delay of the gate driving i and the arrival times of the inputs to the gate:

15. 15 Definitions The slack is the difference between the required and arrival times. Positive slack means that the circuit meets timing. Negative slack means that the circuit is not fast enough.

16. Example Nodes annotated with arrival times. If the outputs are all required at 200 ps, the circuit has 60 ps of slack. 16

17. 17 Timing Optimization In most designs there will be many logic paths are already fast enough for the timing goals of the system. However, there will be a number of critical paths that limit the operating speed of the system and require attention to timing details.

18. Example c_in a0 b0 a1 b1 s0 s1 c_out mux Length 5 Length 1 ripple carry adder 1 0

19. 19 Timing Optimization The critical paths can be affected at four main levels: –The architectural/microarchitectural level – The logic level – The circuit level – The layout level

20. 20 Microarchitecture Level Requires a broad knowledge of both the algorithms that implement the function and the technology being targeted, –Many gate delays fit in a clock cycle, –How fast memories are accessed, –How long signals take to propagate along a wire.

21. Microarchitecture Level Trade-offs at the microarchitectural level include: – the number of pipeline stages, –

22. Microarchitecture Level –Trade-offs at the microarchitectural level include: –the number of execution units (parallelism), and –the size of memories.

23. 23 Logic Level Trade-offs include : –Types of functional blocks (e.g., ripple carry vs. lookahead adders),

24. Logic Level Trade-offs include : –The number of stages of gates in the clock cycle,

25. Logic Level Trade-offs include : The fan-in and fan-out of the gates.

26. Logic Level Trade-offs include : –The transformation from function to gates and registers can be done by experience Remember, however, that no amount of skillful logic design can overcome a poor microarchitecture.

27. 27 Circuit Level Delay depends on choosing transistor sizes or using other styles of CMOS logic. Finally, delay is dependent on the layout. The floorplan (either manually or automatically generated) is of great importance because it determines the wire lengths that can dominate delay. Good cell layouts can also reduce parasitic capacitance.

28. 28 Transient Response The most fundamental way to compute delay is to: Develop a physical model of the circuit of interest, Write a differential equation describing the output voltage as a function of input voltage and time, and solve the equation. The solution of the differential equation is called the transient response, and the delay is the time when the output reaches V DD /2.

29. 29 Transient Response The differential equation is based on charging or discharging of the capacitances in the circuit. The circuit takes time to switch because the capacitance cannot change its voltage instantaneously. If capacitance C is charged with a current I, the voltage on the capacitor varies as:

30. 30 Transient Response Every real circuit has some capacitance an inverter X1 driving another inverter X2 at the end of a wire. Suppose a voltage step from 0 to VDD is applied to node A and we wish to compute the propagation delay, tpdf, through X1, i.e., the delay from the input step until node B crosses VDD/2.

31. 31 Transient Response These capacitances are annotated as:

32. 32 Transient Response the equivalent circuit diagram in which all the capacitances are lumped into a single C out.

33. 33 Transient Response Before the voltage step is applied, A = 0. N1 is OFF, P1 is ON, and B = VDD. After the step, A = 1. N1 turns ON and P1 turns OFF and B drops toward 0. The rate of change of the voltage VB at node B depends on the output capacitance and on the current through N1:

34. Delay Estimation

35. RC Delay Model We would like to be able to easily estimate delay –Not as accurate as simulation –But easier to ask “What if?” The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay –C = total capacitance on output node –Use effective resistance R –The effective resistance is the ratio of V ds to I ds averaged across the switching interval of interest.

36. 36 RC Delay Model An nMOS transistor of k times unit width has resistance R/k because it delivers k times as much current. A unit pMOS transistor has greater resistance, generally in the range of 2R–3R, because of its lower mobility.

37. 37 Gate and Diffusion Capacitance Use equivalent circuits for MOS transistors –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width (k) Resistance inversely proportional to width (k)

38. Gate and Diffusion Capacitance

39. MOS equationsSlide 39 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

40. Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

41. Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

42. Slide 42 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

43. Slide 43 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance.

44. MOS equationsSlide 44 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder