1. Utopium

2. ● MCU8051 processor ● Several asynchronous examples ● 256 instructions – Some reather complex ● 256 bytes of ram with memory mapped: – Register bank + stack pointer – Accumulator, status flags – Bit addressable regions ● Started development on February 1 st

4. February 6 th

5. February 12 th

6. February 13 th

7. February 17 th

8. Functional development ● 20 days to develop the synchronous version ● Desynchronised ● Dual-rail early output ● Wagging ● 10 days of tuning ● Interesting stuff ● One man month processor ● 12 month of automating the process

9. Instruction Decode ALU Data Memory Controller

10. Instruction Decode ALU Data Memory Controller

11. Instruction Decode ALU Data Memory Controller

12. Instruction Decode ALU Data Memory Controller

13. Instruction Decode ALU Data Memory Controller

14. Instruction Decode ALU Data Memory Controller

15. Instruction Decode ALU Data Memory Controller

16. Instruction Decode ALU Data Memory Controller

17. Instruction Decode ALU Data Memory Controller

18. Instruction Decode ALU Data Memory Controller

19. Instruction Decode ALU Data Memory Controller

20. Instruction Decode ALU Data Memory Controller

21. Performance wrapper ● Keep original structure and functional behaviour ● Design should remain functional in its synchronous form ● Wagging ● With by-passable stages ● Add pipelining ● Add caching ● Instruction cache ● Data cache

22. Latch Logic

23. Latch Logic Latch Logic

24. Latch Logic Latch Logic Latch Logic Latch Logic

25. Latch Logic Latch Logic Latch Logic Latch Logic

26. Latch Logic

27. Latch Logic

28. CPU Inst RA M Data RA M

29. CPU Inst RA M Data RA M CPU MUX

30. Instruction Decode ALU Data Memory Controller

31. Instruction Decode ALU Data Memory Controller Data Memory Controller Data Cache Instruction Cache

32. Instruction cache option 1 ~88 Byte RAM 8 cache lines 8 bytes data + 2 bytes address 1ns+

33. Instruction cache option 2

34. Instruction cache option 3

35. Data cache ● Register bank cache ● 8 registers ● Stack Pointer ● 2 entry stack cache ● Snoops instruction stream – Detects push and call operations ● Flushes one entry ● Allows all instructions to execute in one cycle per instruction stream byte read

36. Comparisons (How to cheat) ● Handshake solutions ● State performance in MHz equivalent – 60.5 MHz – Woot! ● 6 MIPS ● ~100 times faster ● Caltech ● Only measure the performance of 2 instructions – Accumulate and NOP – Don't memory map the accumulator – ~100 MIPS

37. Instruction Decode ALU Data Memory Controller

38. Tape-out ● Implemented in 130nm tech ● 1 st tape-out was “cancelled” ● 2 nd tape-out 22 nd of November