1. 1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2

2. 2 Review Using MatLab (again) Introduction to Digital Electronics Programmable Logic Devices

3. 3 Review - Digital Concept In order to design circuits, we need to understand the nature of the signals in the circuit the operation of the basic components which serve as the building blocks of the circuit

4. 4 Review - FPGA FPGA building blocks: Programmable logic blocks Implement combinatorial and sequential logic Programmable interconnect Wires to connect inputs and outputs to logic blocks Programmable I/O blocks Special logic blocks at the periphery of a device used for external connections

5. 5 Outline Introduction to VHDL Using Xilinx Software

6. 6 Introduction to VHDL

7. 7 VHDL is an International IEEE Standard Specification Language (IEEE 1076-1993) for describing digital hardware VHDL is an acronym for V HSIC (Very High Speed Integrated Circuit) H ardware D escription L anguage

8. 8 VHDL Tasks VHDL enables hardware modeling from the gate to system level VHDL provides a mechanism for digital design and reusable design documentation VHDL Provides a Common Communications Medium

9. 9 VHDL Structure Package Entity Structural Architecture Data Flow Architecture Behavioral Architecture GenericsPortProcess

10. 10 VHDL Example Write VHDL code to design a 4-bit equality comparator Accept to 4 bit words as input and set the output to 1 if the two words are identical Equality Detector A[3:0] B[3:0] equals VHDL Code: -- eqcomp4 is a 4-bit equality comparator entity eqcomp4 is port (a, b: in std_logic_vector(3 downto 0); equals : out std_logic); end eqcomp4; The entity describes the inputs and outputs architecture dataflow of eqcomp4 is begin equals <= ‘1’ when (a = b) else ‘0’; end dataflow; The architecture describes the box

11. 11 VHDL Structure Every VHDL program has three parts: An optional library declaration A required entity description A required architecture implementation library ieee; use ieee.std_logic_1164.all; entity …. is port... end....; architecture... of... Is begin... end...;

12. 12 Entity The entity declaration describes the inputs and outputs of a design ports it contains a description of the device ports (i.e. the pins in the schematic symbol) entity is... end ; EXAMPLE: a 4-bit adder a[3:0] b[3:0] sum[3:0] co add ci entity add4 is port( a, b: in std_logic_vector(3 downto 0); ci: in std_logic; sum: out std_logic_vector(3 downto 0); co: out std_logic); end add4;

13. 13 Ports Each I/O signal in an entity is called a port a port is a data object so it can be assigned values and used in expressions each port must have a name, a direction (mode), and a data type Port names upper/lower case are equivalent first character must be a letter the last character can not be an underscore two underscores in succession are not allowed

14. 14 Mode A mode describes the direction in which data is transferred through a port IN - data goes into the entity but not out OUT - data goes out of the entity but not in (and is not used internally INOUT - data is bidirectional (goes in and out of the entity) BUFFER - data which goes out of the entity but is also fed back to be used internally

15. 15 Data Types There are several data types available. VHDL provides bit and bit_vector types The IEEE Library provides std_logic and std_logic_vector You must tell VHDL to use this library library ieee; use ieee.std_logic_1164.all;

16. 16 Architecture An architecture describes the contents of an entity VHDL has 3 architecture styles which can be used in any combination in an architecture body behavioral data flow structural The same circuit may be described using any of the three body types

17. 17 Behavioral Model The behavioral model describes the operation of the circuit not how it is implemented. It is very similar to a high level language such as C++, JAVA, or PASCAL Its’ basic component is a process statement

18. 18 Process Statement The form of a process statement is: : process ( ) is begin end process ; We will look at each part1 2 3

19. 19 Sensitivity List The variables in the sensitivity list control the process execution If any of the variables change value, the process will execute process (a, b) begin end process If a or b change Then execute these in sequence

20. 20 Variable List VHDL accepts variables and signals A signal is just a wire in the circuit Variables are declared and used inside processes and subprograms They are created at the beginning of a simulation run and retain their value throughout the run

21. 21 Example A simple process block with a variable: process (A) variable EA : integer := -1; begin EA := EA + 1; end process; Variable name Data type Initial value Assignment statement

22. 22 Data Types Variables come in several different data types Integer Real Enumerated array

23. 23 Enumerated Types Define a data type by listing the possible values Assign a variable to the data type

24. 24 Array Type Used to group elements into a single VHDL object

25. 25 Signals vs. Variables The difference between signals and variables: 1. Variables are used within a process. A variable can not be used to communicate between processes. Signals can. 2. Signal assignments are done using <= while variable assignments are done using := 3. Variables assignments are done in 0 time and are executed sequentially. Signal assignments are done via the event queue. 4. In general, signals represent physical wires in the circuit. Variables might or might not represent physical wires. Variables are only used a convenience for describing behavior

26. 26 VHDL Example The behavioral architecture of VHDL is much like any other standard programming language For example, the GCD (Greatest Common Divisor) algorithm could be implemented directly in VHDL Algorithm: Given two numbers A and B subtract the larger from the smaller (the result replaces the larger) until the result is 0

27. 27 Flow Chart Standard flow chart for the GCD algorithm:

28. 28 VHDL Code The VHDL behavioral code: library ieee; use ieee.std_logic_1164.all, ieee.std_logic_arith.all; entity gcd_alg is port ( A, B : inout unsigned(15 downto 0) Y : out unsigned(15 downto 0)); end entity gcd_alg; architecture prog of gcd_alg is signal swap : unsigned(15 downto 0); signal zero : unsigned(15 downto 0) := ‘0000000000000000”; Begin process if ((A /= 0) and (B /= 0) then while (B /= 0) loop while (A >= B) loop A <= A – B; end loop; swap <= A; A <= B; B <= swap; end loop; else A <= zero; end if; Y <= A; end process end architecture prog; to use comparison and arithmetic operators A and B are used on both sides of arithmetic operations

29. 29 Comments The VHDL code on the prior slide will not compile in MAX+PLUS II because MAX+PLUS II does allow a while…loop It will compile on most VHDL systems which means: This code will directly produce GCD hardware

30. 30 Using Xilinx Software

31. 31 Access Xilinx ISE is available on the PCs in the computer science lab It is also free to students Go to the Xilinx web page Download the ISE Webpack

32. 32 Run Xilinx ISE To run ISE double click on the program icon

33. 33 Projects Designs in ISE are called projects To start a new project select file > new project from the main menu Enter name

34. 34 New Source Wizard The New Source Wizard allows you to begin to set up the VHDL code You will be asked to specify the inputs and the outputs

35. 35 Source Code ISE will create a code template

36. 36 Possible Quiz Remember that even though each quiz is worth only 5 to 10 points, the points do add up to a significant contribution to your overall grade If there is a quiz it might cover these issues: What are the 3 major segments of VHDL? What is a process statement? What is a sensitivity list?