1. Development of SSD and DSSD for J-PARC experiment.
Korea_J-PARC workshop
Seoul National University
Joo Changwoo
2011/09/23

2. contents Introduction of SSD system for J-PARC
Two test experiment of SSD
1. ELPH(Sendai) RCNP(Osaka)
Development of SSD
Development of DSSD

3. SSD and APVDAQ system

4. SSD and DAQ system

5. SSD in J-PARC Assigned E03, E07 Test experiment RCNP 2011 Nov
K1.8 beam line 2012 Feb(?)

6. SSD board part
SSD BOARD
Sensor ( 6x6 cm )

7. SSD sensor part
SENSOR
80um pitch p+ strip on 290um deep n-bulk layer

8. APVDAQ system data P C repeater : gender, supply bias voltage
VME module
repeater
SSD
repeater : gender, supply bias voltage
VME module : communicate pc – readout chip
storage of one event data
data
P C

9. SSD and DAQ system

10. Raw data of one readout chip

11. Signal analysis

12. Signal analysis
Maximum height
Timing

13. Test experiment ELHP 2011 Jan RCNP 2011 Feb

14. Test experiment in ELPH(Sendai)

15. Test experiment in ELPH(Sendai)
Experiment configuration
Converter(Cu) SSD#A,B SSD#C,D
gamma-ray
MPPC MPPC2
~1.2GeV electron -> gamma-ray -> e+,e- pair
~800k per spill

16. ELPH - Result (1)
Hit pattern of SSD#A, B
Hit pattern of SSD#C,D

17. ELPH - Result (2) Time resolution of SSD#C Maximum height distribution

18. Test experiment in RCNP (OSAKA)

19. Test experiment in RCNP (OSAKA)

20. Test experiment in RCNP (Osaka)
Experiment configuration
SSD#A,B,C,D
PMT PMT2
proton beam
~100MeV proton beam with 20Hz intensity.

21. RCNP - Result (1)
Hit pattern of SSD#A, B
Hit pattern of SSD#C,D

22. RCNP - Result (2) Time resolution of SSD#A Maximum height distribution

23. 4 hole of pre-collimator
RCNP - Result (3)
collimator
Collimator profile
4 hole of pre-collimator

24. Development of SSD

25. Problem of SSD system Too slow for K1.8 beam line 2 SSD => ~70Hz
Half SSD => ~340Hz
Too slow for K1.8 beam line

26. Data requirement We need Except pedestal, for one signal,
th channel of 128ch
We need
1. pedestal 2. adc 3. sample numb 4.ch numb 5. chip number
Except pedestal, for one signal,
we need 6/2048 ~ 5% size of data

27. Data current of DAQ system
1. trigger
VME
apvdaq module PC
Memory
2. Data save
3. Data read
SSD
SAVING
READING

28. Timeline for 1 event SAVING READING 6~8msec (1SSD) 1. Single event
trigger
SAVING
READING
RESET
2. Real scale
trigger
6~8msec (1SSD)

29. Size of data VME PC 100% 95% 5% unused used SSD massive data
apvdaq module
100% PC
massive
data
SSD
95% 5%
unused used

30. Data suppression by FPGA
VME
apvdaq module 5% PC
SSD
massive
data
95% 5%
dump use

31. Timeline after suppression
1. Before suppression
trigger
6~8msec
reset
2. After suppression
trigger
reset
We expect 70Hz -> 1~2000Hz data taking.

32. Development of DSSD (Double SSD)

33. Space requirement for 4 SSD
Need more than one cm.
SSD A (x)
B (y)
C (x)
D (y)
E07 has 5mm for SSD.

34. DSSD building
By Double Silicon Strip Detector(DSSD), we can detect X-Y position with one circuit board.
We are now collaborating with Prof.Hwanbea Park in Kyungbook university to produce DSSD

35. Dimensions of the AC-DSSD
n-side
p-side
Sensor size
73620 μm x μm
Strip length
71630 μm
35770 μm
Strip width
20 μm
40 μm
Number of strips
512
1024
AC pad
256 μm x 72 μm
DC pad
136 μm x 36 μm
98 μm x 48 μm
Biasing pad
240 μm x 100 μm
Guard-ring pad
Designed values
n-side
p-side
Biasing resistance
8.8 MΩ
Coupling capacitance
247 pF/strip
or 123 pF/strip
By Kha Dongha

36. By Kha Dongha kah@knu.ac.kr
Wafer design
~7cm
Strip direction
DSSD-1
Strip direction
~3.5cm
DSSD-1
Guard-ring pad
adapter
pitch
adapter
pitch
DSSD-2
DSSD-2
DSSD-3
DSSD-3
~70um pitch strip
p-side
n-side
By Kha Dongha

37. By Kha Dongha kah@knu.ac.kr
p-side
73620 μm
Strip length : μm
37760 μm
2-N-sub pad
(7150 x 60)
8x2-Guard-ring pad
(240 x 100)
8x2-Bising pad
1024-DC pad
(98 x 48)
1024-AC pad
(256 x 72)
1024x2-AC pad
Guard-ring pad
By Kha Dongha

38. By Kha Dongha kah@knu.ac.kr
n-side
73620 μm
Strip length : μm
37760 μm
2-N-sub pad
(7150 x 60)
8x2-Guard-ring pad
(240 x 100)
8x2-Bising pad
(240x 100)
1024-DC pad
(98 x 48)
1024-AC pad
(256 x 72)
1024x2-AC pad
Guard-ring pad
By Kha Dongha

39. DSSD sensor produce
dicing
sensors

40. Leak current of DSSD
DIODE
SSD deplation
Depletion

41. DSSD leak current - estimate

42. DSSD leak current - estimate

43. DSSD readout chip assemble
We will pick up better one,
and attach readout chip (apv25) in REPIC

44. Summary We are developing SSD and DSSD
Two test experiment – last winter
1. ELPH(Sendai) RCNP(Osaka)
-> we are preparing next test experiment.
Development of SSD system
-> increase eventrate by FPGA programming
Development of DSSD
-> now producing