1. - TMS - Temperature Monitoring System in Topix Olave Jonhatan INFN section of Turin and Politecnico P PANDA Collaboration Meeting December 9 th 2014 - Forschungszentrum Jülich

2. Jülich, December 2014J. Olave - INFN -2 Outline  Motivation  Requirements  The circuit Architecture  Simulation results  Conclusion and Outlook Motivation Requirements Architecture Simulations Conclusion Outlook

3. Jülich, December 2014J. Olave - INFN -3 Motivation Requirements Architecture Simulations Conclusion Outlook  Test Board for Topix 4

4. Jülich, December 2014J. Olave - INFN -4 Motivation Requirements Architecture Simulations Conclusion Outlook  Test Board for Topix 4 Topix 4 Sensor LM95071

5. Jülich, December 2014J. Olave - INFN -5 Motivation  Test Board for Topix 4 Topix 4 Sensor LM95071 Layout of Topix 4 Motivation Requirements Architecture Simulations Conclusion Outlook

6. Jülich, December 2014J. Olave - INFN -6 Requirements Motivation Requirements Architecture Simulations Conclusion Outlook Voltage supply of 1.2 V CMOS 0.13 um technology Reduced silicon area Working range from 0° C to 100° C Low power consumption Clock frequency 160 MHz Good resolution (± 0.1°C) Calibration system Radiation hardness Digital output BASIC REQUIREMENTS ASIC REQUIREMENTS

7. Jülich, December 2014J. Olave - INFN -7 The Circuit Architecture Motivation Requirements Architecture Simulations Conclusion Outlook

8. Jülich, December 2014J. Olave - INFN -8  Basic idea to design a BandGap Reference (GBR) V1 = V1(T) ΔV1/ ΔT = α1 T + β1 T 2 + …. V2 = V2(T) ΔV2/ ΔT = α2 T + β2 T 2 + …. V REF (T) = k 1 V1(T) + k 2 V2 (T) It is possible to choose k1 and k2 in order to have ΔV REF / ΔT = 0 The T sensor Motivation Requirements Architecture Simulations Conclusion Outlook

9. Jülich, December 2014J. Olave - INFN -9 The T sensor  Basic idea BandGap Reference (GBR) V1 = V1(T) ΔV1/ ΔT = α1 T + β1 T 2 + …. V2 = V2(T) ΔV2/ ΔT = α2 T + β2 T 2 + …. Motivation Requirements Architecture Simulations Conclusion Outlook V REF (T) = k 1 V1(T) + k 2 V2 (T) It is possible to choose k1 and k2 in order to have ΔV REF / ΔT = 0

10. Jülich, December 2014J. Olave - INFN -10 NTC The T sensor Motivation Requirements Architecture Simulations Conclusion Outlook

11. Jülich, December 2014J. Olave - INFN -11 Bandgap Analog to Digital Converter Vt Vref Motivation Requirements Architecture Simulations Conclusion Outlook FIRST STEPS time Voltage [V] 1.2 Vt @ constant T Signal generator Digital Output

12. Jülich, December 2014J. Olave - INFN -12 Bandgap Analog to Digital Converter Vt Vref Digital Output Motivation Requirements Architecture Simulations Conclusion Outlook time Voltage [V] 1.2 Vt @ constant T Ramp Generator Signal generator Vramp information Comparator FIRST STEPS

13. Jülich, December 2014J. Olave - INFN -13 Bandgap Analog to Digital Converter Vt Vref Digital Output Motivation Requirements Architecture Simulations Conclusion Outlook time Voltage [V] 1.2 Vt @ constant T Ramp Generator Signal generator Vramp information MUXMUX Comparator FIRST STEPS

14. Jülich, December 2014J. Olave - INFN -14 Bandgap Analog to Digital Converter Vt Vref Digital Output Motivation Requirements Architecture Simulations Conclusion Outlook time Voltage [V] 1.2 Vt @ constant T Ramp Generator Signal generator Vramp information Counter Register A MUXMUX Register B Adder Devider Adder Offset Comparator FIRST STEPS

15. Jülich, December 2014J. Olave - INFN -15 Bandgap Analog to Digital Converter Vt Vref Digital Output Motivation Requirements Architecture Simulations Conclusion Outlook time Voltage [V] 1.2 Vt @ constant T Ramp Generator Signal generator Vramp information Counter Register A Control Unit MUXMUX Register B Adder Devider Adder Offset Comparator FIRST STEPS

16. Jülich, December 2014J. Olave - INFN -16 Bandgap Analog to Digital Converter Vt Vref Digital Output Motivation Requirements Architecture Simulations Conclusion Outlook time Voltage [V] 1.2 Vt @ constant T Ramp Generator Signal generator Vramp information Counter Register A Control Unit MUXMUX Register B Adder Devider Adder Offset Comparator FIRST STEPS

17. Jülich, December 2014J. Olave - INFN -17 Bandgap Analog to Digital Converter Vt Vref Digital Output Motivation Requirements Architecture Simulations Conclusion Outlook time Voltage [V] 1.2 Vt @ constant T Ramp Generator Signal generator Vramp information Counter Register A Control Unit MUXMUX Register B Adder Devider Adder Offset Comparator FIRST STEPS Vramp Analog Environment Digital Environment

18. Jülich, December 2014J. Olave - INFN -18 Motivation Requirements Architecture Simulations Conclusion Outlook FIRST STEPS Layout View (100 um x 100 um) Schematic View

19. Jülich, December 2014J. Olave - INFN -19 Motivation Requirements Architecture Simulations Conclusion Outlook Simulation results

20. Jülich, December 2014J. Olave - INFN -20  Variation of the supply voltage - ΔV ref / ΔV supply ≈ 1.4 mV/V - ΔV t / ΔV supply ≈ 1.4 mV/V  Variation with the temperature - ΔV ref / ΔT ≈ 10 -2 mV/°C - ΔV T / ΔT ≈ - 1.63 mV/°C ( IMPROVE ) BANDGAP AND SIGNAL GENERATOR Motivation Requirements Architecture Simulations Conclusion Outlook

21. Jülich, December 2014J. Olave - INFN -21  Variation of the supply voltage - ΔV ref / ΔV supply ≈ 1.4 mV/V - ΔV t / ΔV supply ≈ 1.4 mV/V  Variation with the temperature - ΔV ref / ΔT ≈ 10 -2 mV/°C - ΔV T / ΔT ≈ - 1.63 mV/°C ( IMPROVE ) BANDGAP AND SIGNAL GENERATOR SIGNAL AMPLIFICATION  Two stage op amp with single ended output  Good linearity of V T *  ΔV T / ΔT ≈ + 7.3 mV/°C Motivation Requirements Architecture Simulations Conclusion Outlook

22. Jülich, December 2014J. Olave - INFN -22 Motivation Requirements Architecture Simulations Conclusion Outlook RAMP GENERATOR

23. Jülich, December 2014J. Olave - INFN -23 Motivation Requirements Architecture Simulations Conclusion Outlook RAMP GENERATOR

24. Jülich, December 2014J. Olave - INFN -24  ΔV ramp /Δt ≈ 136 mV/us  Good control of the initial value (250 mV)  The time to discharge the capacitor is ≈ 30 ns Motivation Requirements Architecture Simulations Conclusion Outlook RAMP GENERATOR

25. Jülich, December 2014J. Olave - INFN -25  ΔV ramp /Δt ≈ 136 mV/us  Good control of the initial value (250 mV)  The time to discharge the capacitor is ≈ 30 ns COMPARATOR  Two stages folded cascode structure  2 CMOS inverters  offset = 5 mV  supply current = 3.5 uA Motivation Requirements Architecture Simulations Conclusion Outlook RAMP GENERATOR

26. Jülich, December 2014J. Olave - INFN -26 Motivation Requirements Architecture Simulations Conclusion Outlook DIGITAL PART Post PnR simulation

27. Jülich, December 2014J. Olave - INFN -27 Motivation Requirements Architecture Simulations Conclusion Outlook CONCLUSION  The system is able to extract the information as expected  Single analog and digital blocks tested with good results  The Digital layout is done and tested with good results

28. Jülich, December 2014J. Olave - INFN -28 Motivation Requirements Architecture Simulations Conclusion Outlook CONCLUSION OUTLOOK  Conclude the AMS simulations  Use SEU protections for the digital part  Reduce the silicon area used for the digital part  Start with the analog layout to perform more realistic simulations  The system is able to extract the information as expected  Single analog and digital blocks tested with good results  The Digital layout is done and tested with good results

29. Jülich, December 2014J. Olave - INFN -29 THANK YOU FOR YOUR ATTENTION