1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 2 Martin Kittel Sebastian Stieber

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Results Phase 1 Pezaris-Array-Multiplier Ripple-Carry-Adder No Pipelines Mandatory values for FGPA Area A (# of pairs)3203 Frequency f63,12 MHz E avg 0.5155633 Metric921,58 [s]

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Improvements Multiplier: Changed Operands(Metric = 420.0) Replace 0.5-Coefficient-Multiplier with Shifter (Metric = 241.5) Adder: No Changes

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Improvements Approximate results: Error: 0.2499477 Metric: 30.28 New Multiplier: Unique CSA-Tree for each Coefficient Metric: 22.23 Partial Product Generator a b CSA 3:2 CSA 3:2 CSA 3:2 CSA 3:2 CSA 3:2 CSA 4:2 CPA (Ripple Carry)

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Advantages / Disadvantages Pro: Should be smaller Should be faster Contra: Complex routing Partial Product Generator a b CSA 3:2 CSA 3:2 CSA 3:2 CSA 3:2 CSA 3:2 CSA 4:2 CPA (Ripple Carry)

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Improvements Pipelining 3 Stages Metric: 13.36 Mandatory values for FGPA Area A (# of pairs)1993 Frequency f192,1 MHz E avg 0.2499477 Metric13,36 [s]

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Backannotated Design Timing Constraints 7.483 ns Mandatory values for FGPA Area A (# of pairs)1336 Frequency f133,636 MHz E avg 0.2499477 Metric8,63 [s]

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 ToDo Phase 3 Mapping on ASIC

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 Thank you for your attention!