1. Runtime Reconfigurable Network-on- chips for FPGA-based systems Mugdha Puranik Department of Electrical and Computer Engineering mpuranik@rams.colostate.edu

2. Introduction Need of reconfigurable hardware for Embedded System devices Flexibility provided by Field Programmable Gate Arrays (FPGAs) Need to suitable communication architecture Runtime reconfigurable Network-on-chip (NoC)

3. Partial Reconfiguration of FPGA The partial bit files can be downloaded to modify the reconfigurable regions to change the functionality or just some parameters, without compromising the integrity of applications running on other parts Static logic and Reconfigurable logic Partial bitstreams downloaded via Slave SelectMAP, Slave Serial, JTAG, or Internal Configuration Access Port FPGA PRR 1 PRR 2 Static region Static modules Modules: A & B Modules: C & D

4. Design Factors Quantitative Metrics  Throughput  Latency  Area  Interconnect Utilization  Power and energy consumption Crucial Characteristics  Scalability  Extensibility  Modularity

5. Architectures Communication Architectures which support dynamic exchange of hardware modules

6. DyNoC-Dynamic Network-on-chip Packet based NoC 2D array of processing elements and router Routers inside the boundary of the modules are redundant and can be used as additional resources to implement bigger modules S-XY routing

7. CuNoC Enhances the architecture of DyNoC CU receives upto 4 packets at a time and has one buffer for all Determines the transfer schedule according to priority-to-right rule Two types: (1)Classic CU (2) To-give-way Cugw High performance and low area overhead

8. QNoC QNoC also allows dynamic placement of modules in 2D mesh topology and computes path from source to destination during runtime Q-switch : Input registers, Routing Block, Output Logic, Control Logic Yields higher throughput due to additional intelligent logic of Q-switch

9. CoNoChi-Configurable NoC Virtual cut through switches with four equal full duplex links FPGA is partitioned into grid of rectangular subareas Network size and topology can be changed at runtime Supports physical and logical addresses Less number of switches, saves area, reduces latency

10. ReNoC-Reconfigurable NoC Configurability is inserted as a layer between routers and links Energy-efficient topology switches ReNoC is that it uses both energy efficiency of circuit switching and flexibility of packet switching Clock gating and power gating for unused switches and links Compared to static NoC, application specific reconfigurable architecture ReNoC leads to 56% power reduction

11. Dynamic reconfigurability of FPGA to create shortcuts from source to destination Additional I/O port in crossbar TMAP datafolding toolflow to automatically generate RecoNoC  Reduced reconfiguration time  Smaller area RecoNoC

12. Programmable NoC Router RANoC Router architecture of Network on chip (RANoC)  Network processor on chip (NPoC)  Reconfigurable crossbar switch (RCS)  Decoder unit  Arbiter unit  Input buffer and buffer access unit NPoC configures RCS, RCS adapts its topology Compared to a conventional NoC (SoCIN), RANoC is smaller and consumes less power Power efficient, fast adaptable router

13. PNoC Subnets containing router and network nodes, which can be replaced dynamically Router performs circuit switching of the nodes PNoC topologies Routing table is maintained to establish connections between modules Advantages: high communication rates, low latencies, simpler Disadvantages: wasted bandwidth, poor scalability, setup latencies

14. DRNoC: For Fast System Emulation Reconfigurable platform which accelerates the design space exploration Cores are dynamically allocated to REs (Reconfigurable Elements) Different DRNoC configurations are downloaded in FPGA and emulated Advantages  No synthesis needed  Reconfiguration time in range of microseconds  Online traffic measurement allows tracking network dynamics

15. Fault Tolerant Reconfigurable NoC-based SoC Each tile holds a core container and cache memory NoC is circuit switched Tasks are allocated dynamically and identified using tasks identifier Randomness in runtime mapping of tasks and in route selection: tolerant to faults in interconnections and cores User-aware task allocation & cache memory in tiles: runs tasks with higher temporal locality faster

16. Hardwire NoC On Future FPGAs Hardwire NoC to support the dynamic reconfigurability of FPGAs Additional routing resource Advantages  Saves valuable reconfigurable resources  High speed due to high bandwidth  Reduced power consumption  Simplified design

17. Design Flow for NoC-based devices Need: to reduce design and testing time Advantages of automating designing of reconfigurable NoC  efficient resource utilization  reliable and fast verification and design space exploration  effective testing for system debugging

18. Example of Design Flow Phases  Requirement capturing  Interconnections needed  Mapping: Communication architecture  Routing: All routes needed  Placement: Reconfigurable regions in grid  Final solution selection Outputs  XML files-output of every intermediate step  SystemC files-used for simulation  VHDL files-define reconfigurable architecture  Bitstreams-used to configure FPGA

19. Application Mapping To Use Case Execution Reconfigurations needed after mapping of applications executing a particular use case Minimum reconfiguration overhead, area-efficiency, eliminate re-synthesis NoC based MPSoC synthesis Load and compile program codes on processors Possible NoC configurations are stored in controlling processor

20. Conclusion To integrate multiple applications on single FPGA Reconfigurable NoCs- interconnect framework, reconfiguration capabilities, flexibility and performance Guide in deciding one or the other interconnection architecture Motivate development of novel reconfigurable communication architectures