1. TRIO-CINEMA 1 UCB, 2/08/2010 Instrument Interface FPGA David Clarino CINEMA Space Sciences Laboratory University of California, Berkeley

2. TRIO-CINEMA 2 UCB, 2/08/2010 Overview Main Uses Abstracts control of the devices connected to the IIF as register read/writes over I 2 C Buffers high volume data (STEIN, Telemetry) for convenience of DMA over SPI

3. TRIO-CINEMA 3 UCB, 2/08/2010 Overview

4. TRIO-CINEMA 4 UCB, 2/08/2010 Overview MAGIC relays commands from CPU to control MAGIC ADC reads ADC data to register on IIF for CPU read STEIN pulls data from STEIN and buffers it into blocks convenient for DMA Telemetry Frames CCSDS Source Packets into CCSDS Transfer Frames Reed-Solomon Encodes the Transfer Frame

5. TRIO-CINEMA 5 UCB, 2/08/2010 CPU Interface Overview I2C Interface runs at 400 kHz dsPIC can command IIF by writing to/reading from registers different size registers reflect IIF’s organization of data Uses slave address as register address SPI Interface DMA STEIN data from IIF, TLM data to Address (Hex)NameLength (bits)SignalsPage # Telemetry12 0x00 TLMSTART 8 TLMON12 0x01 VCRD 8 12 0x02 MCRD 8 12 0x03 FRMBYTE 8 12 0x04 BFRBYTE 8 12 0x05 FRMPCKT 8 12 0x06 CLCW 32 CLCW13 0x07 FRAMEID 16 FRAMEID13 0x08 FRMDATA 16 FRMDATA13 0x09 FRMHDWEN 8 MCSET, VCSET, IDSET, DATASET13 0x0A ANTARM 8 13 0x0B ANTDEP 8 13 0x0C ANTSTAT 8 14 STEIN 14 0x10 STEINCMD 24 STEINDCMD14 0x11 STEINSTS 8 ATNIN, ATNOUT14 0x12 STEINFLT 8 STEIN_Fault14 0x13 STEINATN 8 14 0x14 STEINON 8 15 0x15 STEINHV 8 15 MAG 15 0x20 MAGCMD 8 15 0x21 MAGDATA 24 MAGDATA17 0x22 BOOMARM 8 17 0x23 BOOMDEP 8 17 0x24 BOOMOUT 8 17 0x25MAGICFLT8Inst_Fault 18

6. TRIO-CINEMA 6 UCB, 2/08/2010 Telemetry (Overview)

7. TRIO-CINEMA 7 UCB, 2/08/2010 Telemetry Framing CCSDS Format 1115 Byte Packet Frame Size 255 Byte RS Codeblock size with maximum interleave of 5 1086 Bytes of Information 518, 518, 50 byte CCSDS Source Packets

8. TRIO-CINEMA 8 UCB, 2/08/2010 Reed-Solomon Encoder Bit-Serial Multiplication Berlekamp’s Bit-Serial Algorithm uses properties of finite-field arithmetic and traces to calculate the check symbol What this translates to is a simple implementation of shift registers and a routing matrix. The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm, Hsu, Reed, et. al Advantages Calculation is faster than iterative processes in the CPU Calculation can happen “on the fly” i.e. you don’t need to know all of the bytes at one time in the codeblock in order. Saves on memory for buffering purposes Outputs data bit-serially. No need to bit serialize data coming out of these encoders Testing Use C++ code to generate a 255 byte codeblock Compare generated codeblock to codeblock generated bit-serially

9. TRIO-CINEMA 9 UCB, 2/08/2010 MAGIC Control (Overview)

10. TRIO-CINEMA 10 UCB, 2/08/2010 MAGIC Control (Overview) Interface CPU writes commands and receives MAG Vectors over I 2 C IIF writes commands and receives MAG Vectors from MAGIC over SPI Two Types of Vector Reads X, Y, Z B-fields from either the outboard or inboard sensors Outboard Temperature Read (Thermistor) CPU polls at most 64 Hz ADC is relatively “dumb” CPU/FPGA need to initiate read. CPU issues pseudo commands that get translated to actual MAGIC commands Advantages: a channel read will only be a single command from the viewpoint of the CPU. Since read is initiated by CPU, relatively easy for CPU to determine what kind of data is returned by MAG

11. TRIO-CINEMA 11 UCB, 2/08/2010 MAGIC Control Flow

12. TRIO-CINEMA 12 UCB, 2/08/2010 STEIN Functionality Current Status CPU initiates all functions IIF Buffers 508 bytes of STEIN data to be transferred to the CPU Future Determine handshake with CPU to offload data Determine handshake with STEIN to pull data

13. TRIO-CINEMA 13 UCB, 2/08/2010 Testing Plan Simulation Presynthesis: verify all VHDL works Post-synthesis: verify synthesized VHDL works Echo test Use CPU to test IIF Implement registers/blocks to bring out internal signals to CPU Interface Test Implement registers/blocks to verify that interface to device works Dummy Test Implement dummy device on FPGA to test interface Real Test Test actual interface to device Same testing procedure for STEIN, MAGIC, Telemetry