1. The AMchip on the AMBoard Saverio Citraro PhD Student University of Pisa & I.N.F.N. Pisa

2. Outline Algorithm Quick overview on FTK Boards AMBoard LAMBoard Configuration and programming phase Dataflow and running

3. Algorithm in principle Perform a massive distributed pattern matching on 64 AMchips Input: 8 serial links at 2 Gbit/s each AMchip The AMBoard with 64 AMchip06 will compare 6550 Tera Word(16 bits)/s After, the pattern matched are sent to the AUX card that provides the Fit Output : 16 serial links, each link from 4 AMchips in daisy chain

4. Boards

5. AMBoard Distribute data to AMchips Collect output from the AMchips Configuration Interface between CPU and AMchips Provide Power to the AMchips Function diagnostic and spy on data flow

6. LAMB: Little AM Board Fan out data to 16 AMchips 200 serial links diff pairs global length 90 m Connect output to the Motherboard Handle AMchips configuration

7. AMBoard + 4 LAMBs

8. Configuration

9. CPU Configuration AMchips Instructions from VME Converted and sent to LAMBs

10. Configuration : From VME to JTAG CPU VME Data BUS 32 bit VME Addr. & Control Chain 0 … Chain 31 12 12 TDI / TDO … TDI / TDO Decodify TMS / TCK / TRST

11. Configuration AMchips Configure SerDes interface: PRBS mode 8b/10b mode Configure logic: Test mode Set threshold and other parameters Store all patterns inside the AMchips

12. Configuration : From VME to JTAG CPU VME Data BUS 32 bit VME Addr. & Control Chain 0 … Chain 31 12 12 TDI / TDO … TDI / TDO VME Slave TMS / TCK / TRST Bottle neck

13. Configuration : From VME to JTAG CPU VME Data BUS 32 bit VME Addr. & Control VME Slave 4 Gbit On Board Flash Memory Data & Conf,

14. Configuration : From VME to JTAG Chain 0 … Chain 31 12 12 TDI / TDO … TDI / TDO Logic TMS / TCK / TRST 4 Gbit Flash Memory Data & Conf,

15. Data Path

16. Dataflow on LAMB Two step of Fan out: First (red squares) multiply the 8 busses in 32 links Second stage (Yellow squares) multiply the 32 links in 128 links The Output is made of 4 links that came from 4 AMchip connected in daisy chain

17. Input Data flow: Test mode CPU Input data from VME Stored in the input FPGA Data sent through FanOuts To 64 AMchips

18. CPU Output Data flow: Test mode Output data of 4 AMchips Merged in one link Output data collected by Output FPGA Data sent to the CPU

19. Input Data flow : Normal mode CPU Input data from AUX Card Received by Input FPGA Spy dataflow through VME Data sent through FanOuts To 64 AMchips

20. Output Data flow: Normal mode CPU Output data of 4 AMchips Merged in one link Output data collected by Output FPGA Spy dataflow through VME Data sent to the AUX Card

21. Running flow diagram

22. Example of running First Event

23. Example of running First Event

24. Example of running First Event Init Event

25. Example of running First Event Init Event Second Event

26. Example of running First Event Init Event Second Event

27. Example of running First Event Init Event Second Event

28. Example of running First Event Init Event Second Event Road End Event

29. Example of running First Event Init Event Second Event Road End Event Third Event

30. Example of running First Event Init Event Second Event Road End Event Third Event

31. Conclusion Use AMchips for parallel and distributed pattern matching How configure 64 chips Dataflow in test and normal mode Running events

32. Any questions? Thanks!