1. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.1 Block diagram of sequential circuit

2. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.2 Synchronous clocked sequential circuit

3. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.3 SR latch with NOR gates

4. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.4 SR latch with NAND gates

5. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.5 SR latch with control input

6. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.6 D latch

7. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.7 Graphic symbols for latches

8. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.8 Clock response in latch and flip-flop

9. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.9 Master–slave D flip-flop

10. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.10 D-type positive-edge-triggered flip-flop

11. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.11 Graphic symbol for edge-triggered D flip-flop

12. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.12 JK flip-flop

13. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.13 T flip-flop

14. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.1 Flip-Flop Characteristic Tables

15. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.14 D flip-flop with asynchronous reset

16. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.15 Example of sequential circuit

17. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.2 State Table for the Circuit of Fig. 5.15

18. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.3 Second Form of the State Table

19. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.16 State diagram of the circuit of Fig. 5.15

20. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.17 Sequential circuit with D flip-flop

21. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.18 Sequential circuit with JK flip-flop

22. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.4 State Table for Sequential Circuit with JK Flip-Flops

23. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.19 State diagram of the circuit of Fig. 5.18

24. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.20 Sequential circuit with T flip-flops (Binary Counter)

25. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.5 State Table for Sequential Circuit with T Flip-Flops

26. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.21 Block diagrams of Mealy and Moore state machines

27. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.22 Simulation output of Mealy_Zero_Detector

28. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.23 Simulation output of HDL Example 5.6

29. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.24 Simulation output of HDL Example 5.7

30. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.25 State diagram

31. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.6 State Table

32. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.7 Reducing the State Table

33. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.8 Reduced State Table

34. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.26 Reduced state diagram

35. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.9 Three Possible Binary State Assignments

36. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.10 Reduced State Table with Binary Assignment 1

37. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.27 State diagram for sequence detector

38. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.11 State Table for Sequence Detector

39. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.28 K-Maps for sequence detector

40. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.29 Logic diagram of a Moore-type sequence detector

41. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.12 Flip-Flop Excitation Tables

42. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.13 State Table and JK Flip-Flop Inputs

43. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.30 Maps for J and K input equations

44. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.31 Logic diagram for sequential circuit with JK flip-flops

45. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.32 State diagram of three-bit binary counter

46. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. Table 5.14 State Table for Three-Bit Counter

47. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.33 Maps for three-bit binary counter

48. Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved. FIGURE 5.34 Logic diagram of three-bit binary counter