1. Memory Organization 1

2.  3 types of memory are used in PIC18 microcontroller devices: Program Memory - Flash Memory Data RAM - Static RAM Data EEPROM - EEPROM 2

3.  As Harvard architecture devices PIC18 MCU assigns data and program to two different memory spaces provides separate buses to them, allows for concurrent access at the same time. 3

4.  One memory space for both program and data.  Limits operating bandwidth 4

5.  Two separate memory spaces for program and data  Increases throughput  Different program and data bus widths are possible 5

6. 6 Program Memory Space. (32 Kbytes / 16KWords) (a portion of this space is on the MCU chip) PIC18 CPU Data Memory Space. (Special Function registers & General Purpose RAM) 16-bit Instruction Bus 12-bit Register Address 8-bit Data Bus 21-bit Program Address

7. 7 Program Memory

8.  Use a 21-bit program counter,  capable of addressing a 2-Mbyte program memory space.  has 32 Kbytes of Flash memory  store up to 16,384 single-word instructions.  PIC18 devices have two interrupt vectors.  The Reset vector address is at 0000h and  the Interrupt vector addresses are at 0008h and 0018h. 8

9.  static RAM (SRAM).  Each register has a 12-bit address,  up to 4096 bytes of data memory.  divided into 16 banks  contain 256 bytes each  Each bank is selected by Bank Select Register BSR )  The data memory contains:  Special Function Registers (SFRs)  General Purpose Registers (GPRs). 9

10.  Used by CPU and peripheral modules for controlling the operation of the device.  Implemented as static RAM.  SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). 10

11.  The SFRs classified into two sets:  “core” device functionality (ALU, Resets and interrupts) and  those related to the peripheral functions.  The SFRs are typically distributed among the peripherals whose functions they control.  Unused SFR locations are unimplemented and read as ‘0’s. 11

12.  banked memory in the GPR area.  This is data RAM, which is available for use by all instructions.  GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area.  GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 12

13.  nonvolatile memory array, separate from the data RAM and program memory  It is not directly mapped in either the register file or program memory space  is indirectly addressed through the Special Function Registers (SFRs).  The EEPROM is readable and writable during normal operation. 13

14.  4 SFRs are used to read and write to the data EEPROM as well as the program memory. They are:  EECON1  EECON2  EEDATA  EEADR  allows byte read and write. 14

15.  When interfacing to data memory block:  EEDATA holds the 8-bit data for read/write  EEADR register holds the address of the EEPROM location being accessed.  A byte write automatically erases the location and writes the new data (erase - before-write).  The write time is controlled by an on-chip timer. 15

16.  Specifies the address of the next instruction to be executed.  The CPU uses the program counter to execute the program instructions one after another.  The PC is 21 bits wide and is contained in three separate 8- bit registers.  The low byte, PCL register, is both readable and writable.  The high byte, PCH register, PC bits; is not directly readable or writable.  The upper byte is called PCU register, PC bits; it is also not directly readable or writable. 16

17.  is a 8-bit working register used for ALU operations, similar to the accumulator in many other microcontrollers  Used as a scrap pad  for Arithmetic & Logical operations  as the source of an operand.  serves as the destination for the result of the instruction execution. 17

18.  5-bit Stack pointer address of 31 levels deep stack.  It is a separate memory location pointed by the special function register STKPTR.  STKPTR always point to the top of the stack and it increments or decrements depending upon CALL/Goto or Return instructions.  Can manipulate the stack pointer, but this is not the same as having a PUSH/POP command. 18

19. Stack Level 31 RESET State; No RAM at this location STKPTR Stack Level 1... Stack Level 0 Stack Grows “Upward” *(++STKPTR) 20 0 19

20.  bit 7:STKFUL: Stack Full Flag bit  1 = Stack full or overflow occurred  0 = Reset or cleared by user software 20 R/C-0 U-0R/W-0 STKFU L STKUN F - SP4SP3SP2SP1SP0 Bit 76543210

21.  bit 6:STKUNF: Stack Underflow Flag bit  1 = Stack underflow occurred  0 = Reset or cleared by user software 21 R/C-0 U-0R/W-0 STKFULSTKUNF- SP4SP3SP2SP1SP0 Bit 76543210

22.  bit 4-0:SP4:SP0:Stack Pointer Location bits  The lower 5 bits of STKPTR (bit 4 to 0) points to the top of the stack.  Bit 7 indicates overflow and  Bit 6 indicates underflow. 22 R/C-0 U-0R/W-0 STKFULSTKUNF- SP4SP3SP2SP1SP0 Bit 76543210

23. 23

24. 24