1. Full-Custom Design …. TYWu

2. Outline Introduction Transistor Process Steps Layout Schematic R/C Design Rules Tools

3. R/C Typical Resistance Values for 0.5 Micron Process  Poly: 4 ohms/square  ndiff: 2 ohms/square  pdiff: 2 ohms/square  metal 1: 0.08 ohms/square  metal 2: 0.07 ohms/square  metal 3: 0.03 ohms/square

4. R/C How to Calculate Wire Resistance Resistance of any size square is constant

5. R/C Wire resistance Exercise R sq =4 L=5 W=2.5 R=? Answer R=R sq * L / W =4 * 5 / 2.5 =8

6. R/C An Example of Resistance Information in a Virtuoso Technology File : electricalRules( characterizationRules( ( sheetRes "METAL1" 0.076 ) ( sheetRes "METAL2" 0.076 ) ( sheetRes "METAL3" 0.076 ) ( sheetRes "METAL4" 0.076 ) ( sheetRes "METAL5" 0.044 ) ) ;characterizationRules ) ;electricalRules :

7. R/C Basic Transistor Parasitic  Gate to source/drain  Basic structure of gate is parallel-plate capacitor  Gate capacitance C g. Determined by active area P-Substrate poly n+ C gs C gd C gb

8. R/C Basic Transistor Parasitic  Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. C gs = C ol W P-Substrate poly n+ C gs C gd C gb

9. R/C Capacitances Formed by P-N Junctions n+ depletion region Substrate bottom-wall capacitance sidewall capacitances

10. R/C Capacitances Formed by P-N Junctions  Typical 0.5 micron diffusion capacitance values n-type:  bottomwall: 0.6 fF/um 2  sidewall: 0.2 fF/um P-type  bottomwall: 0.9 fF/um 2  sidewall: 0.3 fF/um n+ bottom-wall capacitance sidewall capacitances L1 W L2 An Example for N-type: (2*L1+2*W)*0.6+W*L1*0.2

11. R/C Can Couple to Adjacent Wires on Same Layer, Wires on Above/Below Layers metal 2 metal 1 Poly

12. R/C Precise Parasitic Capacitance Includes 3D Field Effect Metal3 Metal2 Metal1

13. R/C Formula of Capacitance  Capacitance = K * f 1 (A) / f 2 (D) Area Distance

14. R/C An Example of Capacitance Information in a xCalibre Technology File : CAPACITANCE CROSSOVER PLATE metal4 metal5 MASK [ PROPERTY C C = 0.0363014 * area() ] : CAPACITANCE NEARBODY metal3 WITH SHIELD metal3 MASK [ PROPERTY C max_width = 3 max_distance = 3 C = length() * (exp(-4.27576 - 0.227378 * (distance())) + 0.024792 / pow(distance(), 0.846884)) * 1.60305 * pow((width1() + width2()) / 2, 0.161101) ] :

15. R/C LPE (Layout Parasitic Extraction) 1D  2D  3D Rough/Fast  ….  Accurate/Slow

16. R/C LPE (Layout Parasitic Extraction)  Extraction of Resistive/Capacitive Networks  Create new nodes with resistance extraction In1 In1_t1 In1_t2

17. R/C Lumped to Ground Coupled Capacitance Coupling Capacitance Lumped to Ground

18. R/C Lumped to Ground Coupled Capacitance  Delay and Peak Noises Coupling Capacitance Lumped to Ground

19. R/C Crosstalk Is a 1st - Order Problem for 0.18 Micron and Below

20. R/C R/C Reduction

21. R/C πModel of Wire

22. R/C Elmore Delay: Nonlinear Delay Model for Delay Calculator

23. R/C Exercise 1Ω1Ω1Ω1Ω 1pF δ=? δ = [1Ω *(1pf+1pf)]+ [1Ω *1pf] = 3

24. R/C Extracted Capacitances in Schematic Spice : CC1 O VSS! 3.22380E-1+6F CC2 O VDD! 3.15840E-16F CC3 I VSS! 6.05184E-16F CC4 I VDD! 5.24466E-16F * *----- TOTAL # OF CAPS FOUND : 4 *----- COMMENTED : 0 *.ENDS 原本的 Schematic LPE 後 Schematic Spice

25. R/C Example for Pre/Post-layout Simulation Pre-sim Post-sim

26. R/C RC Extractor  Cadence Assura

27. R/C RC Extractor  Synopsys Star-RCXT

28. R/C SPEF : *CAP 1 data_in[3]:0 0.500668 2 data_in[3]:1 0.500668 3 data_in[3]:2 0.0604604 4 data_in[3]:3 0.0604604 5 data_in[3]:4 0.0940104 *RES 1 data_in[3]:0 data_in[3]:1 4.01365 2 data_in[3]:2 data_in[3]:3 0.303 3 data_in[3]:4 data_in[3]:5 0.5555 4 data_in[3]:6 data_in[3]:7 2.60075 5 data_in[3]:8 data_in[3]:5 6.4 :

29. R/C DSPF NETLIST_PRINT_CC_TWICE: NO *|NET NETA 0.0010000PF *|I (NETA:F1 I0 A I 0 485.5 11) *|I (NETA:F2 I1 Z O 0 483.5 11) R1 NETA:F1 NETA:F2 12.43 C1 NETA:F1 0 6e-15 C2 NETA:F2 0 3.5e-15 C3 NETA:F1 NETB:F1 5e-16 *|NET NETB 0.007000PF *|P (NETB B 0 32.5 8.3) *|I (NETB:F1 I32 B I 0 554.3 12) RNETB NETB:F1 1032 C4 NETB 0 5e-15 C5 NETB:F1 0 1.5e-15 :

30. R/C RC Extractor  Star-RCXT

31. R/C RC Extractor  Mentor xCalibre

32. Outline Introduction Transistor Process Steps Layout Schematic R/C Design Rules Tools

33. Design Rules Definition of Layout Layers

34. Design Rules Widths 0.6um 0.3um metal 3 metal 2 metal 1 pdiff/ndiff poly 0.2um

35. Design Rules Rules for Vias and Contacts  Types of contacts and vias: metal1/diff, metal1/poly, metal1/metal2 0.2 0.3 0.1

36. Design Rules Spacings Rules  Diffusion/diffusion:0.3  Poly/poly: 0.2  Poly/diffusion: 0.1  Via/via: 0.2  Metal1/metal1: 0.3  Metal2/metal2: 0.4  Metal3/metal3: 0.4 0.2

37. Design Rules Transistors 0.2 0.3 0.1 0.3 0.2 0.5

38. Design Rules An Example (TSMC 0.18um Process)  Minimum and maximum width of a contact 0.220 um (A)  Minimum space between two contacts 0.250 um (B) B A A

39. Design Rules An Example (TSMC 0.18um Process)  Minimum clearance between OD region and 1.5V transistor gate poly = 0.400 um (D)  Minimum extension of OD region beyond 2.5V transistor gate poly = 0.400 um (E)

40. Design Rules Metal Pitch Consists of Two Parts  The width of the metal line and  The minimum amount of space needed to separate one line from another.

41. Design Rules Pitch and Spacing

42. Design Rules A fully-contacted metal pitch (via-on-via) aligns all the vias on a grid so that metal pitch is the width of, and spacing between, any two vias. Line-on-via spacing permits tighter spacing by staggering the via. Thus, metal pitch is the width of the via/2+metal/2 plus the spacing between via and adjacent line.

43. Design Rules Exercise Via-on-via pitch = ? Line-on-via pitch = ? Via-on-via pitch = 0.3+0.1+0.1+0.2 =0.7 Line-on-via pitch =(0.3+0.1+0.1)/2+0.2/2+0.2 =0.25+0.1+0.2 =0.55 0.3 0.1 0.2 0.1 0.3 0.2

44. Design Rules Dummy Metal (TSMC 0.18um Process)  Metal Density is calculated as total metal layout area / chip area  Metal Density > 30 %

45. Design Rules Metal Slot (TSMC 0.18um Process)  The metal slot must be placed for releasing stress of wide metal line. The wide metal is defined as being > 35 um wide. Only bonding pad areas are excepted.

46. Design Rules Antenna Effect  Unconnected wires act as “antennas” that pick up electrical charge.  The longer the wires, the more the charge.

47. Design Rules Antenna Effect  Wires are always shorted in the highest metal layer.  0.18 (0.13) um technology: the maximum length of an “antenna” wire is 500 um (20 um).

48. Design Rules Antenna Effect  Depends on the gate size Aggressive down sizing makes the problem worse!  Depends on length of the part of the wire that is “un- shorted” (that is, not connected to a diffusion drain area)

49. Design Rules Fixing Antenna Effect Using Diodes  Insert a diode cell next to each input. Costs significant area

50. Design Rules Fixing Antenna Effect through Jumpers  The idea: Force a routing pattern that “shoots up” to the highest layer as soon as possible.

51. Design Rules Fixing Antenna Effect through Jumpers

52. Design Rules An Example of Design Rules in a Laker Technology File width [[opt]] { { inLayerA [inLayerB] Relation1 Num1 [Num2] [angle angOpt] \ [lenA Relation2 Num3 [Num4]] [lenB Relation3 Num5 [Num6]] } [outLayer] [{ edgeaOut outLayerA }] [{ edgebOut outLayerB }] [ { output { outCell l-num d-num } } ] [genCell { LayoutCellName { LayerName PurposeName } } ] } width { { NP lt 1.6 } NP123 { output { NP123 23 0 } } } ; width of NP should >= 1.6um

53. Design Rules An Example of Design Rules in a Calibre Technology File METAL_WIDTH { // Metal width check. Metal width must be greater than or // equal to 3 microns except where metal length exceeds 5 // microns; in that case, metal width must be greater than or // equal to 4 microns. long_metal = metal LENGTH > 5 // Layer definition; // not output to results db INTERNAL long_metal < 4 // Output to results db short_metal = metal NOT LENGTH > 5 //Layer definition INTERNAL short_metal < 3 //Output to results db }

54. Design Rules Electrical Rule Check (ERC)  Check for Connection Characteristic of Devices  Check for Connection Characteristic of Layers  Check for Open/Short of Interconnect Wires  Check for Charge/Discharge Path of Node

55. Design Rules Examples  Check for Open Circuit Fault  Check for Short Circuit Fault vdd vss

56. Design Rules LVS (Layout vs. Schematic) ? Spice (CDL)GDSII

57. Design Rules Tools  Mentor Calibre  Synopsys Hercules  Cadence Dracula (≥ 0.35um)

58. Design Rules Calibre

59. Design Rules Calibre  Layer definition for layer operation n_diff = diffusion NOT p_dope //n+ diffusion p_diff = diffusion AND p_dope //p+ diffusion n_tap = n_diff NOT OUTSIDE n_well //n-tap areas not_n_tap = n_diff OUTSIDE n_well //areas which are not n-taps p_tap = p_diff OUTSIDE n_well //p-tap areas not_p_tap = p_diff NOT OUTSIDE n_well //areas not p-taps n_gate = poly AND not_n_tap //n-channel gates p_gate = poly AND not_p_tap //p-channel gates nsd = not_n_tap NOT n_gate //n-source/drain regions psd = not_p_tap NOT p_gate // p-source/drain regions

60. Design Rules Calibre  All Calibre rule files are written in the Standard Verification Rule Format (SVRF) language  There is generally no need to have separate rule files for DRC, LVS, and PEX.  All verification rules can coexist in a single rule file.

61. Design Rules Calibre  LVS

62. Design Rules Calibre  An example for a rule file GROUP mask_check // all the DRC checks for mask-level data poly_width poly_spacing dr2w dr2s dr3 dr5 dr6w dr7 dr11pp dr11np dr12 dr13 dr14 dr17np dr17pp minimum_contact dr20 dr21 dr23 dr26 dr28 dr29 dr30 dr31 poly_width { @Poly width must be 1.25 INTERNAL poly < 1.25 } poly_spacing { @Poly spacing must be 2 EXTERNAL poly < 2 }