1. Alternative tracking technologies: Depleted CMOS Marcos Fernández García IFCA-CSIC & Departamento de Física Moderna (Universidad de Cantabria) [also visiting scientist at CERN-SSD]

2. 2 ▪ From Hybrid to CMOS Pixels ▪ Depleted Monolithic Active Pixels (DMAPS) HVCMOS HRCMOS SOI ▪ DMAPs radiation hardness ▪ Conclusions Summary

3. 3 Hybrid model Advantages: 1) Both parts (sensor and RO chip) can be optimized separately Sensor: radiation hardness RO chip: Digest & process high rates (~Mhz/mm2) 2) RO chip allows for complex signal processing: Zero supression Storage of hits during decision time (L1 latency) Disadvantages: 1) Large material budget (~3% X 0 in ATLAS& CMS) due to: sensor, RO chip, flex capton, support, cooling, services. 2) Module production: bump bonding and flip chipping is complex and expensive See: N. Wermes, arXiv:1509.09052v1, 30 Sep 2015

4. 4 Monolithic CMOS pixels Advantages 1) Low cost, as long as standard commercial process not modified 2) Large area 3) Mechanically simpler 4) Smaller pixel size achievable (not limited by BB size) 5) They can be thinned down to 50  m Disadvantages (of MAPs, triple well MAPS, INMAPs...) 1) Limited radiation hardness if charge is collected by diffusion 2) Normally “simpler” RO (MAPs do not allow PMOS transistors): signal is multiplexed I Peric, Habilitation Thesis

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6. 6 New developments Simplicity: Keep monolotithic Cost:Stick to commercial CMOS technology Radiation Hardness: Drift as charge collection mechanism → deplete HR-CMOS CMOS on SOI HV HV-CMOS ATLAS HV/HR-collaboration HVCMOS: I. Peric et al. HRCMOS: N. Wermes et al. SOI: H.Pernegger et al

7. 7 HVCMOS Uses commercial high-voltage (  120V) CMOS technology (used in industry as HV switches). This HV is applied to a low resistivity substrate (  ~10  cm) Expected 10  m depletion at 100 V → Charge can be collected by drift Expected 900 e-h pairs → built-in preamp is needed To avoid damage to transistors both, NMOS and PMOS are “embedded” in a Deep N Well (DNW). Any complex signal processing can be implemented inside. The DNW works both as a substrate for transistors and as the signal collection region. Nearly 100% fill factor: – Charge carriers do not have to travel long before being collected → reduced trapping impact. We need to quantify this radiation hardness – Capacitance due to big collecting region increases noise of CSA Two development strategies: 1) Conservative: drop in replacement of current sensors. Build preamplifier in sensor chip and capacitively couple to RO chip 2) Liberal: Go fully monolithic and totally replace RO chip

8. 8 HVCMOS (strip configuration, ILC?) Strip configurations (existing already an ATLAS demonstrator) using larger pixels (in one direction) and daisy chaining several of them in a strip. Advantage: Hit position resolution along the strip is possible, encoding hit position in amplitude of pulse Current source I 0 in each pixel connected to address line. After particle hit, pixel comparator turns off the switch. Current I in reduction proportional to hit position CCPD: Capacitively Coupled Pixel Detector Calculated glue thickness 8  m

9. 9 HVCMOS radiation hardness Contributed by IFCA-UC, together with CERN-SSD within RD50 collaboration Studied scenario for HL-LHC. Neutrons: 0, 1e15, 7e15, 2e16 n eq /cm 2. Samples kept at room T Charge collection studied using dedicated diode conceived for edge-TCT measurements M. Fernandez et al, JINST paper (to be submitted)

10. 10 HVCMOS: radiation hardness Transients at the center of the diode and 30  m below it. Fast collection → Seems like drift Running charge: accumulated charge as a function of integration time Distinct signature of diffusion is unveiled

11. 11 Collected charge profile Q(z): Unirrad & 1e15 very similar Deepest depletion for 7e15 Note: Laser power variation 1% (RMS) HVCMOS: radiation hardness T=-20C -80 V 5 ns int time Normalized to 1 (unirrad) T=-20C 5 ns int time, 90  m deep Results below are averages over max 3 measurements

12. 12 Charge collection referred to unirradiated detector 7E15 collects double than unirrad 2E16 comparable to 1e15 Effective space charge calculated from depletion depth (FWHM) Laser beam width~10  m Non-negligible impact on FWHM estimation Error in FWHM due to finite beam width used to calculate displayed error bars HVCMOS: radiation hardness

13. 13 SOI-CMOS: radiation hardness SOI resitivity 100  cm Irradiation campaign: Neutrons 0, 1e13, 5e13 neq/cm2 RS measurements: irradiated sample to 5e13 neq/cm2 collects more charge than the irradiated sample to 1e13 neq/cm2, giving a possible indication for Acceptor Removal Effect. First eTCT characterizations of unirradiated detectors show different growth of depletion region bulk- and sidewise Bias ring=100V, p-field structure floating Bias ring=100V, p-field structure 100V S. Fernandez et al, IWORid proc. JINST paper

14. 14 Conclusion s Growing surface of tracking systems, upgrades, complexity of hybridization, cost of traditional hybrid sensors make monolithic solutions very attractive. Dream scenario: a CMOS tracker could be replaced by a new one at low cost DMAPs (HVCMOS, HRCMOS,SOI...) candidate detectors HVCMOS is the only one not requiring modified CMOS process HRCMOS → needs HR wafers (k  cm), triple wells, backbiasing SOI → moderate resistivity 100  cm HVCMOS radiation hardness tested until 2e16 – Unexpected effect observed: acceptor removal – For the first time observed, the collected charge after 7e15 bigger than unirradiated! – Irradiation of low resistivity substrates seem to have benefitial effect in: - Charge collection - Depletion depth – After 2e16 detector performance very similar to unirradiated SOI and HRCMOS technologies also being pursued and actively tested (mainly ATLAS) Very novel detector: measurement → paper. 1 paper submitted, 1 pending for internal corrections 2 more to com (biasing, proton irradiation)

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16. 16 Size is important...

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